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기능 Avionics CAN Controller
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HI-3112 데이터시트, 핀배열, 회로
HI-3110, HI-3111, HI-3112, HI-3113
May 2016
Avionics CAN Controller
with Integrated Transceiver
GENERAL DESCRIPTION
The HI-3110 is a standalone Controller Area Network
(CAN) controller with built in transceiver. The device
provides a complete, integrated, cost-effective solution for
avionics applications implementing the CAN 2.0B
specification and can be configured to comply with both the
ARINC 825 (General Standardization of CAN Bus Protocol
for Airborne Use) and CANaerospace standards. The HI-
3110 is capable of transmitting and receiving standard
data frames, extended data frames and remote frames.
The internal transceiver allows direct connection to the
CAN bus without using external components and coupled
with the host Serial Peripheral Interface (SPI), results in
minimal board space.
The HI-3110 provides the optimum solution for
applications where minimum host (MCU) overhead is
required, filtering unwanted messages using a maskable
identifier filter and storing up to 8 messages in the receive
FIFO. A flexible interrupt scheme allows real time
servicing of the FIFO by the host, if required.
Transmissions are handled using an 8 message transmit
FIFO. A Transmit Enable pin can be used by the host to
initiate a transmission. The device also provides monitor
or listen-only mode, low power sleep mode, loopback
mode for self-test and a re-transmission disable capability
(necessary to implement TTCAN protocol).
The HI-3111 is a digital only version of the HI-3110 (no
transceiver). This version provides a “protocol only”
solution for customers who wish to use an external
transceiver and may be used in situations where the
customer requires galvanic isolation between the bus and
digital protocol logic. The HI-3112 provides an option of a
CLKOUT pin instead of a SPLIT pin, which may be used as
the main system clock or as a clock input for other devices
in the system. Finally, the HI-3113 provides all options
(both CLKOUT and SPLIT pins) in a very compact QFN-44
package.
The HI-3110 family is available in industrial and full
extended temperature ranges, with a “RoHS compliant”
lead-free option. The design has been independently
validated by C&S group, GmbH, an ISO/IEC 17025
accredited test house. A copy of the test report is available
from Holt on request.
FEATURES
· Implements CAN version 2.0B with programmable bit
rate up to 1Mbit/sec. ISO 11898-5 compliant.
· Configurable to support ARINC 825 and
CANaerospace Standards.
· Serial Peripheral Interface (SPI) (20MHz).
· Standard, Extended and Remote frames supported.
· 8 maskable identifier filters.
· Filtering on ID and first two data bytes for both
Standard and Extended Identifiers.
· Loopback mode for self-test.
· Monitor (Listen-only) and Low Power Sleep Modes
with automatic wake-up possible.
· 8-message Transmit and Receive FIFOs.
· Internal 16-bit free running counter for time tagging of
transmitted or received messages.
· Permanent dominant timeout protection.
· Short Circuit Protection of -58V to + 58V on CAN_H,
CAN_L and SPLIT pins (ISO 11898-5).
· Re-transmission disable capability.
· Transmit Enable pin.
· Industrial and Full Extended temperature ranges
supported:
Industrial: -40oC to + 85oC.
Extended: -55oC to + 125oC.
PIN CONFIGURATION (Top View)
VLOGIC 1
OSCOUT 2
OSCIN 3
GP1 4
GP2 5
TXEN 6
SPLIT 7
GND 8
CANL 9
3110PSI
3110PST
3110PSM
18 INT
17 MR
16 CS
15 SO
14 SI
13 SCK
12 STAT
11 VDD
10 CANH
18-Pin Plastic SOIC - WB Package
(DS3110 Rev. J)
HOLT INTEGRATED CIRCUITS
www.holtic.com
05/16




HI-3112 pdf, 반도체, 판매, 대치품
HI-3110, HI-3111, HI-3112, HI-3113
FUNCTIONAL OVERVIEW
The HI-3110 is the first single chip product to integrate both
the CAN (Controller Area Network) protocol and analog
interface transceiver on a single IC. The protocol conforms
to CAN version 2.0B and is compliant with ISO 11898-
1:2003(E) specification. The transceiver is compliant with
ISO 11898-5 specification.
Configuration options include an internal Loopback mode
that does not disturb the bus, a Monitor only mode, and a
Sleep mode that includes an option to either wake up
automatically when data is present on the bus, or by host
command. The following sections describe some of the key
features.
SPI and REGISTERS
To minimize the footprint, a 20 MHz standard four wire SPI
(Serial Peripheral Interface) is provided to manage the flow
of data between the host microcontroller and the HI-3110.
Complete messages are loaded and retrieved with single
SPI op codes. On the receive side, SPI op code options may
be used to retrieve the whole message or just the data. An
option to include a time tag or no time tag may also be
specified. On the transmit side, each message can be
assigned an identifier which allows monitoring of the
Transmit History FIFO to confirm the successful completion
of a transmission along with the time stamp. In addition the
transmitter logic automatically assembles the message
frame based on the data presented.
BIT TIMING
Bit timing is controlled with standard CAN options. These
include control of the Resychronization Jump Width (SJW),
Prop delay Phase Seg 1 (TSeg1), Phase Seg 2 (TSeg2), the
number of samples, and the derivation of Tq from the system
clock using a prescaler. The maximum bit rate is 1 MBit/sec.
Upon reset, the chip automatically enters Initialization mode
which allows programming of the Bit Timing before entering
Normal mode.
RECEIVER
The receiver state machine automatically handles all CAN
2.0B protocol requirements. The receiver supports eight
sets of filters and masks and each allows filtering of a full
CAN ID (extended or not) and two bytes of data. Even when
filtering is enabled, message data is always accessible as
received via the Temporary Receive Buffer, and retrievable
by SPI op codes 0x42 and 0x44.
If the Filter/Mask option is set (FILTON bit in Control Register
1), only messages that match one of the 8 stored data
patterns are passed into the FIFO. Note that the Mask option
allows certain bits of the programmed filter bits to be “don't
care.” If the Filter/Mask option is not set, then all valid
messages are passed to the FIFO. When the FIFO is full (8
completed messages received), the next received message
is not loaded in the FIFO.
ERROR CONTROL
Errors are detected per ISO 11898-1:2003(E) and
detections are counted and used by the protocol state
machines. Active, Passive, and Bus Off conditions are
managed per the CAN standard. A configuration bit is
provided to allow automatic recovery from Bus Off.
STATUS and INTERRUPTS
The Message Status Register, MESSTAT, provides
information about the current state of the receiver and
transmitter operation. In addition, the Interrupt Flag
Register, INTF, monitors 8 operational conditions, any or all
of which may be directed to the INT pin by enabling bits in the
Interrupt Enable Register, INTE. Similarly, the Status Flag
Register, STATF, bits reflect the status of selected FIFO and
Error properties. Any or all of these conditions may be
directed to the STAT pin by setting the enable bits in the
Status Flag Enable Register, STATFE.
To provide additional hardwired flag options, the GP1 and
GP2 pins may also be programmed to reflect any of the
Interrupt or Status Flag bits.
TRANSMITTER
The transmitter state machine automatically handles all
CAN 2.0B protocol requirements. Messages for
transmission are first loaded into a FIFO and transmission
may start upon availability of data in the FIFO. Assertion of
the TXEN pin or configuration bits in Control Register 1 allow
either continuous transmission until the FIFO is empty or
only one message from the FIFO at a time. One shot (no
retry) transmission may also be enabled by setting the OSM
and TX1M bits. SPI op codes are provided to clear the
Transmit FIFO and to abort transmission.
OSCILLATOR and TIME TAG
A configuration bit allows a choice for the source of the
system clock. Either the on-board crystal oscillator may be
selected or an external clock may be provided at the OSCIN
pin.
On product versions with the CLKOUT pin, a programmable
division of the system clock is provided. The clock source for
the 16 bit Time Tag Counter is derived from a separate
programmable division of the system clock. SPI op codes
provide for reading and resetting the Time Tag Counter.
TRANSCEIVER
The HI-3110 contains an integrated transceiver operating
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HI-3112 전자부품, 판매, 대치품
HI-3110, HI-3111, HI-3112, HI-3113
combinations greater than or equal to <1 0 0 0> specify 8
bytes of data.
The remaining fields of the extended data frame (Data field,
CRC field, acknowledge field, EOF field and IFS field) are
constructed in the same way as the standard frame format.
REMOTE FRAME
The remote frame is shown in figure 4. The function of
remote frames is to allow a receiver which periodically
receives certain types of data to request that data from the
transmitting source. The identifier of the remote frame must
be identical to the identifier of the requested transmitting
node’s data frame and the data length code (DLC) should be
equal to the DLC of the requested data. Simultaneous
transmission of remote frames with the same identifier
and different DLCs will lead to unresolvable collisions
on the bus. For this reason, ARINC 825 strongly
discourages the use of remote frames.
The format of a remote frame is identical to the format of the
corresponding data frame except the remote frame has no
data payload. Remote frames and data frames are
distinguished by a recessive RTR bit in the remote frame.
This means if a receiver sends a remote frame and the
sending node transmits at the same time, the sending node
(with a dominant RTR bit) will win arbitration and the
requesting node will receive the desired data immediately.
ERROR FRAME
The error frame is shown in figure 5. Any node detecting an
error generates an error frame. The error frame consists of
two fields, the error flag field and the error delimiter. The
type of error flag field depends on the error status of the
node, error-active or error-passive (see below). An error-
active node generates an active error flag and an error-
passive node generates a passive error flag.
Active Error Flag: An active error flag consists of 6
consecutive dominant bits. This condition violates the rule
of bit-stuffing and causes all other nodes on the bus to
generate error flags, known as echo error flags. Therefore,
the error flag field will consist of the superposition of different
error flags sent by individual nodes, resulting in a minimum
of 6 and maximum of 12 consecutive dominant bits. The
error flag field is followed by the error delimiter, consisting of
8 recessive bits.
Passive Error Flag: A passive error flag consists of 6
recessive bits. This is followed by the 8 recessive bits of the
error delimiter. Therefore, an error frame sent by an error-
passive node consists of 14 consecutive recessive bits.
Since this will not disturb the bus, a transmitting node will
continue to transmit unless it detects the error itself, or
another error-active node detects the error.
it must wait for 6 consecutive bits of equal polarity before
completing the error flag. If the passive error flag is
generated by a transmitter, the bit stuffing rule is violated and
it will cause other nodes to generate error flags. Two
exceptions to this rule are
a) the passive error flag starts during arbitration and another
node prevails and begins transmitting, and
b) the error flag starts less than 6 bits before the end of the
CRC sequence and the last bits of the CRC sequence all
happen to be recessive.
OVERLOAD FRAME
The overload frame is shown in figure 6. It has the same
format as the active error frame, consisting of an overload
flag field and an overload delimiter. The overload flag
consists of 6 consecutive dominant bits. This condition
violates the rule of bit-stuffing and causes all other nodes on
the bus to generate echo flags, similar to the active error flag
echos. Therefore, the overload flag field will consist of the
superposition of different overload flags sent by individual
nodes, resulting in a minimum of 6 and maximum of 12
consecutive dominant bits. The overload flag is followed by
the overload delimiter, consisting of 8 recessive bits.
An overload frame, unlike an error frame, can only be
generated during the interframe space. There are two types
of overload frame:
1) Reactive Overload Frame, resulting from
a) detection of a dominant bit during the first or second bit of
intermission,
b) detection of a dominant bit at the last (seventh) bit of EOF
in received frames, or
c) detection of a dominant bit at the last (eighth) bit of an error
delimiter or overload delimiter.
The reactive overload frame is started one bit after detecting
any of the above dominant bit conditions.
2) Requested Overload Frame. A node which is unable to
begin reception of the next message due to internal
conditions may request a delay by transmitting a maximum
of two consecutive overload frames. The requested
overload frame must be started at the first bit of an expected
intermission.
Note 1): The HI-3110 will never initiate an overload frame
unless reacting to one of the conditions in case 1) above.
Note 2): Initiation of overload frames is prohibited by ARINC
825 since they increase the network loading.
Notes: If the passive error flag is generated by a receiver, it
cannot prevail over any other activity on the bus. Therefore,
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부품번호상세설명 및 기능제조사
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