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기능 100-MHz 32-bit RX MCUs
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R5F562TADDFH 데이터시트, 핀배열, 회로
DATASHEET
RX62T Group, RX62G Group
Renesas MCUs
R01DS0096EJ0200
100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC (3 S/H circuits, double data
register, amplifier, comparator): two units, 10-bit ADC one unit, the three ADC units are
Rev.2.00
Jan 10, 2014
capable of simultaneous 7-ch. sampling, 100-MHz PWM (two three-phase complementary
channels and four single-phase complementary channels or three three-phase
complementary channels and one single-phase complementary channel)
Features
32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Accumulator handles 64-bit results (for a single
instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
Divider (fastest instruction execution takes two CPU
clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
Background JTAG debugging plus high-speed tracing
Operating voltage
Single 3.3- or 5-V supply; 5-V analog supply is possible
with 3.3-V products
Low-power design and architecture
Four low-power modes
On-chip main flash memory, no wait states
100-MHz operation, 10-ns read cycle
No wait states for reading at full CPU speed
64-Kbyte/128-Kbyte/256-Kbyte capacities
For instructions and operands
User code programmable via the SCI or JTAG
On-chip data flash memory
Max. 32 Kbytes, reprogrammable up to 30,000 times
Erasing and programming impose no load on the CPU.
On-chip SRAM, no wait states
8-Kbyte/16-Kbyte SRAM
For instructions and operands
DMA
DTC: The single unit is capable of transfer on multiple
channels
Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External crystal oscillator or internal PLL for operation at
8 to 12.5 MHz
Internal 125-kHz LOCO for the IWDT
Detection of main oscillator stoppage (for IEC 60730
compliance)
Independent watchdog timer
(for IEC60730compliance)
125-kHz LOCO clock operation
Software is incapable of stopping the robust WDT.
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
PLQP0112JA-A 20×20mm, 0.65mm pitch
PLQP0100KB-A 14×14mm, 0.5mm pitch
PLQP0080JA-A 14×14mm, 0.65mm pitch
PLQP0064KB-A 10×10mm, 0.5mm pitch
PLQP0064GA-A 14x14 mm, 0.8mm pitch
Up to 7 communications interfaces
1: CAN (compliant with ISO11898-1), incorporating 32
mailboxes
3: SCIs, with asynchronous mode (incorporating noise
cancellation), clock-synchronous mode, and smart-card
interface mode
1: I2C bus interface, capable of SMBus operation
1: RSPI
1: LIN
Up to 16 16-bit timers
8: 16-bit MTU3: 100-MHz operation, input capture,
output compare, two three-phase complementary PWM
output channels, complementary PWM imposing no load
on the CPU, phase-counting mode
4: 16-bit GPT: 100-MHz operation, input capture, output
compare, four complementary single-phase PWM output
channels, or one three-phase complementary PWM
output channel and one single-phase complementary
PWM output channel, complementary PWM imposing no
load on the CPU, operation linked with comparator (for
counting and control of PWM-signal negation), detection
of abnormal oscillation frequencies (for IEC 60730
compliance)
4: 16-bit CMT
Generation of delays in PWM waveforms (only for
the RX62G Group)
The timing with which signals on the 16-bit GPT PWM
output pin rise and fall can be controlled with an accuracy
of up to 312 ps (in operation at 100 MHz).
Three A/D converter units for 1-MHz operation,
for a total of 20 channels
Three units are capable of simultaneous sampling on
seven channels
Self diagnosis (for IEC60730 compliance)
8: Two 12-bit ADC units: three sample-and-hold circuits,
double data registers, amplifier, comparator
12: Single 10-bit ADC unit
CRC (cyclic redundancy check) calculation unit
Monitoring of data being transferred (for IEC 60730
compliance)
Monitoring of data in memory (for IEC 60730
compliance)
Up to 61 input–output ports and up to 21 input-only
ports
PORT registers: Monitoring of output ports (for IEC
60730 compliance)
Operating temp. range
–40C to +85C
–40C to +105C
Page 1 of 134




R5F562TADDFH pdf, 반도체, 판매, 대치품
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
1. Overview
Table 1.1
Outline of Specifications (3 / 5)
Classification
Timers
Communications
Module/Function
General PWM timer
(GPT/GPTa)
Compare match
timer (CMT)
Watchdog timer
(WDT)
Independent
watchdog
timer (IWDT)
Serial
communications
interface (SCIb)
I2C bus interface
(RIIC)
Description
16 bits x 4 channels
Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for
all channels
Clock sources independently selectable for all channels
2 input/output pins per channel
2 output compare/input capture registers per channel
For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
In output compare operation, buffer switching can be at peaks or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
Synchronizable operation of the several counters
Modes of synchronized operation (synchronized, or displaced by desired times for phase
shifting)
Generation of dead times in PWM operation
Through combination of three counters, generation of automatic three-phase PWM
waveforms incorporating dead times
Starting, clearing, and stopping counters in response to external or internal triggers
Internal trigger sources: output of the internal comparator detection, software, and
compare-match
The frequency-divided system clock (ICLK) can be used as a counter clock for
measuring timing of the edges of signals produced by frequency-dividing the low-speed
on-chip oscillator clock signal dedicated to IWDT (to detect abnormal oscillation).
PWM delay generation can control the timing with which signals on the two PWM output
pins for each channel rise and fall with an accuracy of up to 1/32 times the period of the
system clock (ICLK) (only for GPTa).
(16 bits x 2 channels) x 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
8 bits x 1 channel
Select from among eight counter-input clock signals (PCLK/4, PCLK/64, PCLK/128,
PCLK/512, PCLK/2048, PCLK/8192, PCLK/32768, PCLK/131072)
Switchable between watchdog timer mode and interval timer mode
14 bits x 1 channel
Counter-input clock: low-speed on-chip oscillator dedicated to IWDT
3 channels
Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
Multiprocessor communications
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Noise cancellation (only available in asynchronous mode)
1 channel
Communications formats
I2C bus format/SMBus format
Master/slave selectable
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 4 of 134

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R5F562TADDFH 전자부품, 판매, 대치품
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX62T Group, RX62G Group
1. Overview
Table 1.2
Functions of RX62T Group and RX62G Group Products (1 / 2)
Functions
RX62G Group
RX62T Group
Pin number
Data transfer
Data transfer
controller (DTC)
112 Pins
100 Pins
Interrupt
Input on the NMI pin
controller (ICU) Input on the IRQ pins (8)
Timers
Multi-function timer
pulse unit 3 (MTU3)
General PWM timer —
(GPT)
General PWM timer
(GPTa)
MTU3/GPT
complementary
PWM pin
12
Port output enable 3
(POE3)
(POE pins: 5)
112 Pins
100 Pins
80 Pins
(R5F562T
xGDFF)
80 Pins
*1
*1
6
Compare match
timer (CMT)
Watchdog timer
(WDT)
Independent
watchdog timer
(IWDT)
Communication Serial
function
communications
interface (SCI)
I2C bus interface
(RIIC)
CAN module (CAN)
(as an optional
function)
LIN module (LIN)
Serial peripheral
interface (RSPI)
12-bit A/D converter (S12ADA)
(4 ch. x 2 units)
Simultaneous
sampling on three
channels
(2 units)
Programmable gain (3 ch. x 2 units)
amplifier
Window comparator (3 ch. x 2 units)
10-bit A/D converter (ADA)
(12 ch.)
(4 ch.)
CRC calculator (CRC)
I/O ports
I/O pins
61 55 61 55 44 44
Input pins
21 21 21 21 13 13
64 Pins
(4)
(POE pins:
3)
37
9
R01DS0096EJ0200 Rev.2.00
Jan 10, 2014
Page 7 of 134

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