Datasheet.kr   

PL613-21 데이터시트 PDF




PhaseLink Corporation에서 제조한 전자 부품 PL613-21은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 PL613-21 자료 제공

부품번호 PL613-21 기능
기능 Programmable 3-PLL Clock IC
제조업체 PhaseLink Corporation
로고 PhaseLink Corporation 로고


PL613-21 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 9 페이지수

미리보기를 사용할 수 없습니다

PL613-21 데이터시트, 핀배열, 회로
PL613-21
Ultra Low Power PicoPLL, Programmable 3-PLL Clock IC
FEATURES
Designed for PCB Space Savings with 3 Low-
Power Programmable PLLs
Ultra Low-Power Consumption
Ultra-Low Power Down Mode, <5A Typical
CLK1 Capable of Generating 32.768kHz
Individual Output Buffer VDD Pins for Flexible
Output Voltages, 1.8V to 3.3V, ±10%
Individual PLL Power Down Control
Output Frequency (based on VDD_CORE voltage):
o <65MHz @ 1.8V operation
o <90MHz @ 2.5V operation
o <125MHz @ 3.3V operation
Input Frequency:
o Fundamental Crystal: 10MHz to 40MHz
o Reference Input: 10MHz to 200MHz
Active Low or Hi-Z Disabled Output State
1.8V to 3.3V, ±10% Core Power Supply
1.8V to 3.3V, ±10% Buffer Power Supply
Operating Temperature Ranges:
o Commercial: 0C to 70C
o Industrial: -40C to 85C
Available in GREEN/RoHS Compliant 3x3 QFN
Package
PIN CONFIGURATION
PDB4
CLK4
VDD4
PDB1
12 11 10 9
13 8
14 P61321 7
XXX(I)
15 6
LLL
16 5
1 23 4
CLK3
PDB2_3
VDD2_3
CLK2
QFN-16L Package
DESCRIPTION
The PL613-21 is an advanced three PLL design based on PhaseLink’s PicoPLL, the world’s smallest
programmable clock technology. This advanced technology allows the PL613-21 to fit in to a small 3x3mm QFN
package for high performance, low-power, small form-factor applications. By using the individual output buffer
VDD pins, the PL613-21 can support multiple output voltage requirements. In addition, CLK1 has the ability to
generate kHz outputs and is ideal for generating 32.768kHz outputs.
The unique power down features of the PL613-21 allows the user to shut down individual PLLs when the corresponding
clock output is disabled using the PDB pins. The output drive strength can be individually programmed on each output to
Low (4mA), Standard (8mA) or High (16mA) drive. In addition, the disabled state of the clock outputs can be
programmed as Hi-Z or Active Low.
Besides its small form factor and multiple outputs that can reduce overall system costs, the PL613-21 offers superior
phase noise, jitter and power consumption performance.
2880 Zanker Road, San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 8/11/10 Page 1




PL613-21 pdf, 반도체, 판매, 대치품
PL613-21
Ultra Low Power PicoPLL, Programmable 3-PLL Clock IC
VDD_CORE vs. VDD4 DESIGN CONSIDERATIONS AND REQUIREMENTS
Power supply voltage (DC) at VDD4 must be greater than or equal to power supply voltage (DC) at VDD_CORE (VDD4
VDD_CORE). If VDD4 = VDD_CORE, VDD4 and VDD_CORE must be supplied from the same power supply.
The ramp time of VDD_CORE and VDD4 must be between 100µS and 250mS from 0V to 90% of VDD target. These
VDD ramps need to be monotonic rising.
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
Decoupling and Power Supply Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like
ringing).
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Design long traces (<1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections
bouncing back and forth.
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1F for
designs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load.
Crystal
Cst
Cpt
XIN
1
XOUT
8
Cpt
CST – Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset.
This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator.
CPT – Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers
frequency offset.
2880 Zanker Road, San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 8/11/10 Page 4

4페이지










PL613-21 전자부품, 판매, 대치품
PL613-21
Ultra Low Power PicoPLL, Programmable 3-PLL Clock IC
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
Operating Drive Level
Metal Can Crystal
Shunt Capacitance
ESR Max
Small SMD Crystal
Shunt Capacitance
ESR Max
SYMBOL
FXIN
CL (xtal)
C0
ESR
C0
ESR
MIN TYP MAX UNITS
10 40 MHz
15 pF
0.1 1.0 mW
5.5 pF
40 Ω
2.5 pF
60 Ω
2880 Zanker Road, San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 8/11/10 Page 7

7페이지


구       성 총 9 페이지수
다운로드[ PL613-21.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
PL613-21

Programmable 3-PLL Clock IC

PhaseLink Corporation
PhaseLink Corporation
PL613-21

Programmable 3-PLL Clock IC

Micrel
Micrel

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵