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PL613-05 데이터시트 PDF




PhaseLink Corporation에서 제조한 전자 부품 PL613-05은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 PL613-05 자료 제공

부품번호 PL613-05 기능
기능 3 Output Clock IC
제조업체 PhaseLink Corporation
로고 PhaseLink Corporation 로고


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PL613-05 데이터시트, 핀배열, 회로
(Preliminary)PL613-05
1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
FEATURES
DESCRIPTION
Designed for PCB space savings with 3 low-power The PL613-05 is an advanced triple PLL design
Programmable PLLs and 3 distinct clock outputs.
based on PhaseLink’s PicoPLL, world’s smallest
Low-power consumption (<10µA when PDB is
activated)
programmable clock, technology. This flexible
programmable architecture is ideal for high
Output frequency:
performance, low-power, low-cost applications. When
o <110MHz @ 1.8V operation
using the power down (PDB) feature the PL613-05
o <166MHz @ 2.5V operation
consumes less than 10 µA of power. Besides its small
o <200MHz @ 3.3V operation
form factor and 3 distinct outputs that can reduce
Input frequency:
o Fundamental Crystal: 10MHz to 40MHz
o Reference Input: 10MHz to 200MHz
overall system costs, the PL613-05 offers superior
phase noise, jitter and power consumption
performance.
Programmable I/O pins can be configured as
Output Enable (OE), Power Down (PDB) inputs, or
Clock output.
Disabled outputs programmable as HiZ or
Active Low
Single 1.8V to 3.3V, ±10% power supply
Operating temperature range from -40°C to 85°C
Available in GREEN/RoHS compliant SOP-8L package.
PIN CONFIGURATION
XIN, FIN
CLK2, OEM^, PDB^
VDD
CLK0
1
2
3
4
8 XOUT
7 VDD
6 CLK1
5 GND
SOP-8L
^ Denotes internal pull up
BLOCK DIAGRAM
FREF
XIN/FIN
XOUT
Xtal FREF Programmable VCO1
OSC
PLL1
Odd/Even
Divider
(5-bits)
OEM
PDB
Programmable Function
Programmable VCO2
PLL2
FREF
Programmable VCO3
PLL3
Odd/Even
Divider
(5-bits)
Odd/Even
Divider
(5-bits)
%1, %2,
%4, %8
%1, %2,
%4, %8
CLK1
CLK0
CLK2, OEM, PDB
2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 1




PL613-05 pdf, 반도체, 판매, 대치품
(Preliminary)PL613-05
1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like
ringing).
- Design long traces (<1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections
bouncing back and forth.
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1µF for
designs using frequencies < 50MHz and 0.01µF for
designs using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
(Typical buffer impedance 20Ω)
50Ω line
To CMOS Input
Series Resistor
Use value to match output buffer impedance to
50Ω trace. Typical value 30Ω
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load.
Crystal
Cst
Cpt
XIN
1
XOUT
8
Cpt
CST – Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset.
This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator.
CPT – Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers
frequency offset.
2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 4

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PL613-05 전자부품, 판매, 대치품
(Preliminary)PL613-05
1.8V-3.3V PicoPLL, 3-PLL, 200MHz, 3 Output Clock IC
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOP-8L
Symbol
A
A1
A2
b
C
D
E
H
L
e
Dimension in MM
Min. Max.
1.35 1.75
0.10 0.25
1.25 1.50
0.33 0.53
0.19 0.27
4.80 5.00
3.80 4.00
5.80 6.20
0.40 0.89
1.27 BSC
EH
D
A2 A
A1 C
eb
L
2880 Zanker Road, San Jose, CA 95134, (Tel) 408-571-1668, (Fax) 408-571-1688 www.phaselink.com Rev 09/16/11 Page 7

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