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PDF RK30xx Data sheet ( Hoja de datos )
| Número de pieza | RK30xx | |
| Descripción | Technical Reference Manual | |
| Fabricantes | Rockchip | |
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RK30xxTechnical Reference ManualRev2.0
RK30xx
Technical Reference Manual
Revision 1.0
Feb. 2012
High Performance and Low-power Processor for Digital Media Application
1
1 page  
RK30xxTechnical Reference ManualRev2.0
7.2 Function Description ..............................................................145
7.3 Register description、 ............................................................145
Chapter 8 Embedded Processor: Cortex-A9 ...........................................255
8.1 Overview .............................................................................255
8.2 Block Diagram ......................................................................256
8.3 Function description ..............................................................256
8.4 Register description ...............................................................256
8.4.1 Registers Summary ........................................................256
8.4.2 Detail Registers Description .............................................260
8.5 Application Notes ..................................................................292
8.5.1 Address filtering.............................................................292
8.5.2 L2 Cache initialization .....................................................292
8.5.3 L2 ram latency programming ...........................................293
8.5.4 L2 data ram mutiplexing .................................................294
Chapter 9 AXI interconnect.................................................................295
Chapter 10 DMAC0(DMA Controller).....................................................296
10.1 Overview............................................................................296
10.2 Block Diagram ....................................................................296
10.3 Function Description ............................................................297
10.3.1 Introduction ................................................................297
10.3.2 Operating states ..........................................................298
10.4 Register Description.............................................................298
10.4.1 Register summary ........................................................298
10.4.2 Detail Register Description.............................................301
10.5 Timing Diagram...................................................................314
10.6 Interface Description ...........................................................314
10.7 Application Notes ................................................................315
10.7.1 Using the APB slave interfaces .......................................315
10.7.2 Security usage .............................................................315
10.7.3 Programming restrictions...............................................319
10.7.4 Unaligned transfers may be corrupted .............................320
10.7.5 Interrupt shares between channel...................................320
10.7.6 Instruction sets ............................................................321
10.7.7 Assembler directives .....................................................322
10.7.8 MFIFO usage ...............................................................322
Chapter 11 DMAC1(DMA Controller).....................................................323
11.1 Overview............................................................................323
11.2 Block Diagram ....................................................................323
11.3 Function Description ............................................................324
11.4 Register Description.............................................................324
High Performance and Low-power Processor for Digital Media Application
5
5 Page 
RK30xxTechnical Reference ManualRev2.0
28.3.5 PCM late1 mode ...........................................................972
28.3.6 PCM late2 mode ...........................................................972
28.3.7 PCM late3 mode ...........................................................973
28.4 Register description .............................................................973
28.4.1 Register Summary........................................................973
28.4.2 Detail Register Description.............................................974
28.5 Timing Diagram...................................................................985
28.5.1 Master mode ...............................................................985
28.5.2 Slave mode .................................................................985
28.6 Interface description ............................................................986
28.7 Application Notes ................................................................987
Chapter 29 I2S/PCM1/2 Controller (2 channel) ......................................989
29.1 Overview............................................................................989
29.2 Block Diagram ....................................................................990
29.3 Function description.............................................................990
29.3.1 I2S normal mode .........................................................991
29.3.2 I2S left justified mode...................................................991
29.3.3 I2S right justified mode.................................................992
29.3.4 PCM early mode ...........................................................992
29.3.5 PCM late1 mode ...........................................................992
29.3.6 PCM late2 mode ...........................................................993
29.3.7 PCM late3 mode ...........................................................993
29.4 Register description .............................................................994
29.4.1 Register Summary........................................................994
29.4.2 Detail Register Description.............................................994
29.5 Timing Diagram................................................................. 1004
29.5.1 Master mode ............................................................. 1004
29.5.2 Slave mode ............................................................... 1005
29.6 Interface description .......................................................... 1006
29.7 Application Notes .............................................................. 1007
Chapter 30 SPDIF transmitter ........................................................... 1009
30.1 Overview.......................................................................... 1009
30.2 Block Diagram .................................................................. 1009
30.3 Function description........................................................... 1010
30.3.1 Frame Format ............................................................ 1010
30.3.2 Sub-frame Format ...................................................... 1011
30.3.3 Channel Coding.......................................................... 1011
30.3.4 Preamble .................................................................. 1012
30.4 Register description ........................................................... 1012
30.4.1 Register Summary...................................................... 1012
30.4.2 Detail Register Description........................................... 1013
30.5 Interface description .......................................................... 1015
High Performance and Low-power Processor for Digital Media Application
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet RK30xx.PDF ] | |
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