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September 2002

FDS3692

N-Channel PowerTrench® MOSFET

100V, 4.5A, 60mΩ

Features

• rDS(ON) = 50mΩ (Typ.), VGS = 10V, ID = 4.5A

• Qg(tot) = 11nC (Typ.), VGS = 10V

• Low Miller Charge

• Low QRR Body Diode

• Optimized efficiency at high frequencies

• UIS Capability (Single Pulse and Repetitive Pulse)

Formerly developmental type 82745

Applications

• DC/DC converters and Off-Line UPS

• Distributed Power Architectures and VRMs

• Primary Switch for 24V and 48V Systems

• High Voltage Synchronous Rectifier

• Direct Injection / Diesel Injection Systems

• 42V Automotive Load Control

• Electronic Valve Train Systems

Branding Dash

5

1

2

3

4

SO-8

MOSFET Maximum Ratings TA = 25°C unless otherwise noted

Symbol

VDSS

VGS

ID

EAS

PD

TJ, TSTG

Parameter

Drain to Source Voltage

Gate to Source Voltage

Drain Current

Continuous (TA = 25oC, VGS = 10V, RθJA = 50oC/W)

Continuous (TA = 100oC, VGS = 10V, RθJA = 50oC/W)

Pulsed

Single Pulse Avalanche Energy (Note 1)

Power dissipation

Derate above 25oC

Operating and Storage Temperature

Thermal Characteristics

RθJA

RθJA

RθJC

Thermal Resistance, Junction to Ambient at 10 seconds (Note 3)

Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3)

Thermal Resistance, Junction to Case (Note 2)

Package Marking and Ordering Information

Device Marking

FDS3692

Device

FDS3692

Package

SO-8

Reel Size

330mm

54

63

72

81

Ratings

100

±20

4.5

2.8

Figure 4

171

2.5

20

-55 to 150

Units

V

V

A

A

A

mJ

W

mW/oC

oC

50 oC/W

85 oC/W

25 oC/W

Tape Width

12mm

Quantity

2500 units

©2002 Fairchild Semiconductor Corporation

FDS3692 Rev. B

Typical Characteristics TA = 25°C unless otherwise noted

200 7

100

10µs

STARTING TJ = 25oC

10

100µs

1

0.1

0.01

OPERATION IN THIS

AREA MAY BE

LIMITED BY rDS(ON)

SINGLE PULSE

TJ = MAX RATED

TC = 25oC

1ms

10ms

100ms

1s

0.1 1 10 100 300

VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 5. Forward Bias Safe Operating Area

STARTING TJ = 150oC

1

If R = 0

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

0.1

0.01 0.1 1 10

tAV, TIME IN AVALANCHE (ms)

100

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

30 PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

25 VDD = 15V

20

15 TJ = 150oC

10 TJ = 25oC

TJ = -55oC

5

0

3.5

4.0 4.5 5.0 5.5 6.0

VGS , GATE TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics

6.5

30

TA = 25oC

25

VGS = 10V

20

15

10

5

0

0

VGS = 6V

VGS = 7V

VGS = 5V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

0.5 1.0 1.5

VDS , DRAIN TO SOURCE VOLTAGE (V)

2.0

Figure 8. Saturation Characteristics

70

VGS = 6V

65

60

55

VGS = 10V

50

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

45

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

ID, DRAIN CURRENT (A)

Figure 9. Drain to Source On Resistance vs Drain

Current

2.5

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

2.0

1.5

1.0

0.5

-80

VGS = 10V, ID = 4.5A

-40 0 40 80 120

TJ, JUNCTION TEMPERATURE (oC)

160

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

©2002 Fairchild Semiconductor Corporation

FDS3692 Rev. B

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the

thermal resistance of the heat dissipating path determines

the maximum allowable device power dissipation, PDM, in an

application.

Therefore the application’s ambient

temperature, TA (oC), and thermal resistance RθJA (oC/W)

must be reviewed to ensure that TJM is never exceeded.

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

PDM

=

-(--T----J---M-------–----T----A-----)

RθJA

(EQ. 1)

In using surface mount devices such as the SO8 package,

the environment in which it is applied will have a significant

influence on the part’s current and maximum power

dissipation ratings. Precise determination of PDM is complex

and influenced by many factors:

maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using

Equation 2. The area, in square inches is the top copper

area including the gate and source pads.

Rθ J A

=

64 +

-------------2---6---------------

0.23 + Area

(EQ. 2)

The transient thermal impedance (ZθJA) is also effected by

varied top copper board area. Figure 22 shows the effect of

copper pad area on single pulse transient thermal

impedance. Each trace represents a copper pad area in

square inches corresponding to the descending list in the

graph. Spice and SABER thermal models are provided for

each of the listed pad areas.

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,

the board and the environment they are in.

Copper pad area has no perceivable effect on transient

thermal impedance for pulse widths less than 100ms. For

pulse widths less than 100ms the transient thermal

impedance is determined by the die and package.

Therefore, CTHERM1 through CTHERM5 and RTHERM1

through RTHERM5 remain constant for each of the thermal

models. A listing of the model component values is available

in Table 1.

200

RθJA = 64 + 26/(0.23+Area)

150

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 21

defines the RθJA for the device as a function of the top

copper (component side) area. This is for a horizontally

positioned FR-4 board with 1oz copper after 1000 seconds

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Fairchild device

Spice thermal model or manually utilizing the normalized

100

50

0.001

0.01

0.1

1

AREA, TOP COPPER AREA (in2)

10

Figure 21. Thermal Resistance vs Mounting

Pad Area

150

COPPER BOARD AREA - DESCENDING ORDER

0.04 in2

120 0.28 in2

0.52 in2

0.76 in2

90 1.00 in2

60

30

0

10-1

100 101 102

t, RECTANGULAR PULSE DURATION (s)

Figure 22. Thermal Impedance vs Mounting Pad Area

103

©2002 Fairchild Semiconductor Corporation

FDS3692 Rev. B

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