Si5317 데이터시트 PDF

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Si5317

PIN-CONTROLLED 1–711 MHZ JITTER CLEANING CLOCK

Features

 Provides jitter attenuation for any clock  Selectable output clock signal

frequency

format: LVPECL, LVDS, CML or

 One clock input / two clock outputs

CMOS

 Input/output frequency range:

 Single supply: 1.8, 2.5, or 3.3 V

1–711 MHz

 Loss of lock and loss of signal

 Ultra low jitter: 300 fs

alarms

(12 kHz–20 MHz) typical

 VCO freeze during LOS/LOL

 Simple pin control interface

 On-chip voltage regulator with high

 Selectable loop bandwidth for jitter

PSRR

attenuation: 60 Hz–8.4 kHz

 Small size: 6 x 6 mm, 36-QFN

 Meets OC-192 GR-253-CORE jitter  Wide temperature range: –40 to

specifications

+85 ºC

Applications

 Data converter clocking

 Wireless infrastructure

 Networking, SONET/SDH

 Switches and routers

 Medical instrumentation

 Test and measurement

Description

The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications

that require jitter attenuation without clock multiplication. The Si5317 accepts a

single clock input ranging from 1 to 711 MHz and generates two low jitter clock

outputs at the same frequency. The clock frequency range and loop bandwidth are

selectable from a simple look-up table. The Si5317 is based on Silicon

Laboratories' 3rd-generation DSPLL® technology, which provides jitter attenuation

on any frequency in a highly integrated PLL solution that eliminates the need for

external VCXO and loop filter components. The DSPLL loop bandwidth is user

selectable, providing jitter performance optimization at the application level.

Functional Block Diagram

Ordering Information:

See page 40.

Pin Assignments

Rev. 1.1 4/11

Copyright © 2011 by Silicon Laboratories

Si5317

Si5317

1. Electrical Specifications

Table 1. Recommended Operating Conditions

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Temperature Range

Supply Voltage

Symbol

TA

VDD

Test Condition

3.3 V nominal

2.5 V nominal

Min Typ Max Unit

–40 25

85 ºC

2.97 3.3 3.63 V

2.25 2.5 2.75 V

1.8 V nominal

1.71 1.8 1.89 V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 2. DC Characteristics

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Supply Current (Supply

current is independent of

VDD)

Symbol

IDD

CKIN Input Pin

Input Common Mode

Voltage

(Input Threshold Voltage)

VICM

Input Resistance

Input Voltage Level Limits

Single-ended Input Voltage

Swing

CKNRIN

CKNVIN

VISE

Test Condition

LVPECL Format

622.08 MHz Out

All CKOUTs Enabled1

LVPECL Format

622.08 MHz Out

Only 1 CKOUT Enabled1

CMOS Format

19.44 MHz Out

All CKOUTs Enabled2

CMOS Format

19.44 MHz Out

Only CKOUT1 Enabled2

1.8 V ± 5%

2.5 V ± 10%

3.3 V ± 10%

Single-ended

See note 3

fCKIN < 212.5 MHz

See Figure 2.

fCKIN > 212.5 MHz

See Figure 2.

Min Typ Max Units

— 251 279

mA

— 217 243

mA

— 204 234

mA

— 194 220

mA

0.9 —

1.0 —

1.1 —

20 40

0—

0.2 —

0.25 —

1.4

1.7

1.95

60

VDD

—

—

V

V

V

k

V

VPP

VPP

Notes:

1. LVPECL outputs require VDD > 2.25 V.

2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most

designs, an external resistor voltage divider is recommended.

3. No overshoot or undershoot.

4 Rev. 1.1

Si5317

Table 2. DC Characteristics (Continued)

(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)

Parameter

Symbol

Test Condition

Min Typ Max Units

LVCMOS Output Pins

Output Voltage Low

VOL

IO = 2 mA

VDD = 1.62 V

IO = 2 mA

VDD = 2.97 V

Output Voltage High

VOH

IO = –2 mA

VDD = 1.62 V

IO = –2 mA

VDD = 2.97 V

Single-Ended Reference Clock Input Pin XA (XB with cap to gnd)

——

——

VDD – 0.4 —

VDD – 0.4 —

0.4

0.4

—

—

V

V

V

V

Input Resistance

XARIN

XTAL/RefCLK

— 12 —

Input Voltage Level Limits

XAVIN

RATE[1:0] = LM, ML, MH, or

HM

0

— 1.2

k

V

Input Voltage Swing

XAVPP

0.5 — 1.2 VPP

Differential Reference Clock Input Pins (XA/XB)

Input Resistance

XA/XBRIN

XTAL/RefCLK

— 12 —

Differential Input Voltage

Level Limits

XA/XBVIN

RATE[1:0] = LM, ML, MH, or

HM

0

— 1.2

k

V

Input Voltage Swing

XAVPP/XBVPP

0.5 — 2.4 VPP

Notes:

1. LVPECL outputs require VDD > 2.25 V.

2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most

designs, an external resistor voltage divider is recommended.

3. No overshoot or undershoot.

Rev. 1.1

7

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