LTC2246H - ADC

부품번호

LTC2246H 기능

기능

ADC

제조업체

Linear Technology

로고

LTC2246H 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.

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FEATURES

n Sample Rate: 25Msps

n –40°C to 125°C Operation

n Single 3V Supply (2.8V to 3.5V)

n Low Power: 75mW

n 74.5dB SNR

n 90dB SFDR

n No Missing Codes

n Flexible Input: 1VP-P to 2VP-P Range

n 575MHz Full Power Bandwidth S/H

n Clock Duty Cycle Stabilizer

n Shutdown and Nap Modes

n Pin Compatible Family

LTC2246H (14-Bit), LTC2226H (12-Bit)

n 48-Pin (7mm × 7mm) LQFP Package

APPLICATIONS

n Automotive

n Industrial

n Wireless and Wired Broadband Communication

LTC2246H

14-Bit, 25Msps

125°C ADC In LQFP

DESCRIPTION

The LTC®2246H is a 14-bit 25Msps, low power 3V A/D

converter designed for digitizing high frequency, wide

dynamic range signals. The LTC2246H is perfect for

demanding imaging and communications applications

with AC performance that includes 74.5dB SNR and 90dB

SFDR.

DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ)

and no missing codes over temperature. The transition

noise is a low 1LSBRMS.

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.6V

logic.

A single-ended CLK input controls converter operation. An

optional clock duty cycle stabilizer allows high performance

at full speed for a wide range of clock duty cycles.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

REFH

REFL

ANALOG

INPUT

FLEXIBLE

REFERENCE

INPUT

S/H

–

CLOCK/DUTY

CYCLE

CONTROL

CLK

14-BIT

PIPELINED

ADC CORE

CORRECTION

LOGIC

OUTPUT

DRIVERS

OVDD

D13

•

OGND

2246H TA01

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

Typical INL, 2V Range

4096

8192

CODE

12288 16384

2246H TA01b

2246hfb

LTC2246H

DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the speciﬁcations which apply over the full

operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNITS

LOGIC OUTPUTS

OVDD = 3V

COZ

ISOURCE

ISINK

VOH

Hi-Z Output Capacitance

Output Source Current

Output Sink Current

High Level Output Voltage

VOL Low Level Output Voltage

OVDD = 2.5V

VOH High Level Output Voltage

VOL Low Level Output Voltage

OVDD = 1.8V

VOH High Level Output Voltage

VOL Low Level Output Voltage

OE = High (Note 7)

VOUT = 0V

VOUT = 3V

IO = –10μA

IO = –200μA

IO = 10μA

IO = 1.6mA

IO = –200μA

IO = 1.6mA

IO = –200μA

IO = 1.6mA

l 2.7

2.995

2.99

0.005

0.09

0.4

2.49

0.09

1.79

0.09

POWER REQUIREMENTS The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 8)

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNITS

VDD

OVDD

IVDD

PDISS

PSHDN

PNAP

Analog Supply Voltage

Output Supply Voltage

Supply Current

Power Dissipation

Shutdown Power

Nap Mode Power

(Note 9)

SHDN = H, OE = H, No CLK

SHDN = H, OE = L, No CLK

l 2.8 3 3.5

l 0.5 3 3.6

l 25 30

l 75 90

TIMING CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNITS

fS Sampling Frequency

tL CLK Low Time

(Note 9)

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

(Note 7)

l 18.9 20 500

20 500

MHz

tH CLK High Time

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

(Note 7)

l 18.9 20 500

20 500

tAP Sample-and-Hold Aperture Delay

tD CLK to DATA Delay

Data Access Time After OE↓

BUS Relinquish Time

CL = 5pF (Note 7)

(Note 7)

l 1.4

2.7

l 4.3 12

l 3.3 10

Pipeline Latency

5 Cycles

2246hfb

4페이지

LTC2246H

PIN FUNCTIONS

GND (Pins 1, 4, 9, 13, 15, 18, 24, 25, 29, 32, 36, 37,

48): ADC Power Ground.

AIN+ (Pin 2): Positive Differential Analog Input.

AIN– (Pin 3): Negative Differential Analog Input.

REFH (Pins 5, 6): ADC High Reference. Bypass to Pins 7,

8 with a 0.1μF ceramic chip capacitor as close to the pin

as possible. Also bypass to Pins 7, 8 with an additional

2.2μF ceramic chip capacitor and to ground with a 1μF

ceramic chip capacitor.

REFL (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6

with a 0.1μF ceramic chip capacitor as close to the pin

as possible. Also bypass to Pins 5, 6 with an additional

2.2μF ceramic chip capacitor and to ground with a 1μF

ceramic chip capacitor.

VDD (Pins 10, 11, 12, 46, 47): 3V Supply. Bypass to GND

with 0.1μF ceramic chip capacitors.

CLK (Pin 14): Clock Input. The input sample starts on the

positive edge.

SHDN (Pin 16): Shutdown Mode Selection Pin. Connecting

SHDN to GND and OE to GND results in normal operation

with the outputs enabled. Connecting SHDN to GND and

OE to VDD results in normal operation with the outputs at

high impedance. Connecting SHDN to VDD and OE to GND

results in nap mode with the outputs at high impedance.

Connecting SHDN to VDD and OE to VDD results in sleep

mode with the outputs at high impedance.

If the clock duty cycle stabilizer is used, a >1μs high pulse

should be applied to the SHDN pin once the power supplies

are stable at power up.

OE (Pin 17): Output Enable Pin. Refer to SHDN pin

function.

D0-D13 (Pins 19-23, 26-28, 33-35, 38-40): Digital Out-

puts. D13 is the MSB.

OGND (Pin 30): Output Driver Ground.

OVDD (Pin 31): Positive Supply for the Output Drivers.

Bypass to ground with 0.1μF ceramic chip capacitor.

OF (Pin 41): Over/Under Flow Output. High when an over

or under ﬂow has occurred.

MODE (Pin 42): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to GND selects

offset binary output format and turns the clock duty cycle

stabilizer off. 1/3 VDD selects offset binary output format

and turns the clock duty cycle stabilizer on. 2/3 VDD selects

2’s complement output format and turns the clock duty

cycle stabilizer on. VDD selects 2’s complement output

format and turns the clock duty cycle stabilizer off.

SENSE (Pin 43): Reference Programming Pin. Connecting

SENSE to VCM selects the internal reference and a ±0.5V

input range. VDD selects the internal reference and a ±1V

input range. An external reference greater than 0.5V and

less than 1V applied to SENSE selects an input range of

±VSENSE. ±1V is the largest valid input range.

VCM (Pin 44, 45): 1.5V Output and Input Common

Mode Bias. Bypass to ground with 2.2μF ceramic chip

capacitor.

2246hfb

7페이지

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총 18 페이지수

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