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Compact Synchronous Buck Regulators

ISL8002, ISL8002A, ISL80019, ISL80019A

ISL8002, ISL8002A, ISL80019 and ISL80019A are highly

efficient, monolithic, synchronous step-down DC/DC converters

that can deliver up to 2A of continuous output current from a 2.7V

to 5.5V input supply. They use peak current mode control

architecture to allow very low duty cycle operation. They operate

at either 1MHz or 2MHz switching frequency, thereby providing

superior transient response and allowing for the use of small

inductors. They also have excellent stability and provide both

internal and external compensation options.

ISL8002, ISL8002A, ISL80019 and ISL80019A integrate very low

rDS(ON) MOSFETs in order to maximize efficiency. In addition,

since the high side MOSFET is a PMOS, the need for a Boot

capacitor is eliminated, thereby reducing external component

count. They can operate at 100% duty cycle (at 1MHz) with a

dropout of 200mV at 2A output current.

These devices can be configured for either PFM (discontinuous

conduction) or PWM (continuous conduction) operation at light

load. PFM provides high efficiency by reducing switching losses at

light loads and PWM reduces noise susceptibility and RF

interference.

These devices are offered in a space saving 8 pin 2mmx2mm

TDFN lead free package with exposed pad for improved thermal

performance. The complete converter occupies less than

0.10in2 area.

Features

• VIN range 2.7V to 5.5V

• VOUT range is 0.6V to VIN

• IOUT maximum is 1.5A or 2A (see Table 1 on page 3)

• Switching frequency is 1MHz or 2MHz (see Table 1 on

page 3)

• Internal or external compensation option

• Selectable PFM or PWM operation option

• Overcurrent and short circuit protection

• Over-temperature/thermal protection

• VIN Undervoltage Lockout and VOUT Overvoltage Protection

• Up to 95% peak efficiency

Applications

• General purpose point of load DC/DC

• Set-top boxes and cable modems

• FPGA power

• DVD, HDD drives, LCD panels, TV

Related Literature

• See AN1803, “1.5A/2A Low Quiescent Current High

Efficiency Synchronous Buck Regulator”

VIN

GND

+2.7V …+5.5V 1 VIN

C1

22μF

2 EN

EN 3 MODE

PG 4 PG

ISL8002

PAD

9

L1

PHASE 8 1.2μH

C5

22μF

PGND 7

+1.8V/2A

C6

22μF

R1

FB 6 +0.6V 200kΩ 1%

COMP 5

R2

100kΩ 1%

VOUT

GND

R1

=

R2

⎛

⎝

---V----O----

VFB

–

1⎠⎞

FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION

(INTERNAL COMPENSATION OPTION)

(EQ. 1)

100

90

80

70

2.5VOUT

60

1.8VOUT

1.5VOUT

50

1.2VOUT

0.9VOUT

0.8VOUT

400.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

OUTPUT LOAD (A)

FIGURE 2. EFFICIENCY vs LOAD

FSW = 1MHz, VIN = 3.3V, MODE = PFM, TA = +25°C

July 30, 2013

FN7888.2

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL8002, ISL8002A, ISL80019, ISL80019A

Pin Configuration

ISL8002, ISL8002A, ISL80019, ISL80019A

(8 LD 2x2 TDFN)

TOP VIEW

VIN 1

EN 2

MODE 3

PG 4

THERMAL

PAD

(GPAND)

PIN 9

8 PHASE

7 PGND

6 FB

5 COMP

Pin Descriptions

PIN NUMBER SYMBOL

PIN DESCRIPTION

1 VIN The input supply for the power stage of the PWM regulator and the source for the internal linear regulator that provides

bias for the IC. Place a minimum of 10µF ceramic capacitance from VIN to GND and as close as possible to the IC for

decoupling.

2 EN Device enable input. When the voltage on this pin rises above 1.4V, the device is enabled. The device is disabled when

the pin is pulled to ground. When the device is disabled, a 100Ω resistor discharges the output through the PHASE pin.

See Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5 for details.

3

MODE

Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM

mode. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case the MODE pin is left

floating, however, it is not recommended to leave this pin floating.

4 PG Power Good output is pulled to ground during the soft-start interval and also when the output voltage is below regulation

limits. There is an internal 5MΩ internal pull-up resistor on this pin.

5

COMP

COMP is the output of the error amplifier. When COMP is tied high to VIN, compensation is internal. When COMP is

connected with a series resistor and capacitor to GND, compensation is external. See “Loop Compensation Design” on

page 19 for more detail.

6 FB Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. The output voltage is set by

an external resistor divider connected to FB. In addition, the Power Good PWM regulator’s power-good and undervoltage

protection circuits use FB to monitor the output voltage.

7

PGND

Power and analog ground connections. Connect directly to the board GROUND plane.

8

PHASE

Power stage switching node for output voltage regulation. Connect to the output inductor. This pin is discharged by an

100Ω resistor when the device is disabled. See Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5 for details.

9 THERMAL PAD Power ground. This thermal pad provides a return path for the power stage and switching currents, as well as a thermal

(T-PAD) path for removing heat from the IC to the board. Place thermal vias to the PGND plane in this pad.

4 FN7888.2

July 30, 2013

ISL8002, ISL8002A, ISL80019, ISL80019A

Absolute Maximum Ratings

VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)

PHASE . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6V (DC) or 7V (20ms)

EN, COMP, PG, MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V

FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V

Recommended Operating Conditions

VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A

Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Thermal Information

Thermal Resistance (Typical, Notes 4, 5) θJA (°C/W) θJC (°C/W)

2x2 TDFN Package . . . . . . . . . . . . . . . . . . .

71

7

Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379 for details.

5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications TJ = -40°C to +125°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C. Boldface

limits apply over the operating temperature range , -40°C to +85°C.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

(Note 6)

MAX

TYP (Note 6) UNITS

INPUT SUPPLY

VIN Undervoltage Lockout Threshold

VUVLO

Rising, no load

Falling, no load

2.5 2.7 V

2.2 2.4

V

Quiescent Supply Current

IVIN MODE = PFM (GND), FSW = 2MHz, no load at

the output

35 60 µA

MODE = PWM (VIN), FSW = 1MHz, no load at

the output

7 15 mA

MODE = PWM (VIN), FSW = 2MHz, no load at

the output

10 22 mA

Shut Down Supply Current

OUTPUT REGULATION

ISD MODE = PFM (GND), VIN = 5.5V, EN = low

5 10 µA

Feedback Voltage

VFB Bias Current

Line Regulation

Load Regulation

VFB

TJ = -40°C to +125°C

IVFB VFB = 2.7V. TJ = -40°C to +125°C

VIN = VO + 0.5V to 5.5V (minimal 2.7V)

TJ = -40°C to +125°C

See Note 7

0.595

0.589

-120

-0.2

0.600

50

-0.05

< -0.2

0.605

0.605

350

0.1

V

V

nA

%/V

%/A

Soft-Start Ramp Time Cycle

1 ms

PROTECTIONS

Positive Peak Current Limit

IPLIMIT 2A application

3 3.5 4 A

1.5A application

2.1 2.5 2.9 A

Peak Skip Limit

ISKIP

VIN = 3.6, VOUT = 1.8V (See “Applications

Information” on page 19 for more detail)

450 mA

Zero Cross Threshold

-170 -70 30 mA

Negative Current Limit

INLIMIT

-2.3 -1.5 -1 A

Thermal Shutdown

Temperature rising

150 °C

Thermal Shutdown Hysteresis

Temperature falling

25 °C

7 FN7888.2

July 30, 2013

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