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TDA8037

Low power 3V smart card interface

Rev. 1.1 — 17 November 2014

Product data sheet

1. General description

The TDA8037 is the cost efficient successor of the established integrated contact smart

card reader IC TDA8035. It offers a high level of security for the card performing current

limitation, short circuit detection, ESD protection as well as supply supervision. Operating

in 3 V supply domain, the current consumption during the shutdown mode of the contact

reader is very low. It is therefore the ideal component for a power efficient contact reader.

2. Features and benefits

2.1 Protection of the contact smart card

 Thermal and short-circuit protection on all card contacts

 VCC regulation:

 3 V  5 % on 2  220 nF multilayer ceramic capacitors with low ESR

 Current spikes of 40 nA up to 20 MHz, with controlled rise and fall times, filtered

overload detection approximately 120 mA

 Automatic activation and deactivation sequences initiated by software or by hardware

in the event of a short-circuit, card take-off, overheating, VDDhost, VREG and VDD

dropping

 Enhanced card-side ElectroStatic Discharge (ESD) protection of (> 8 kV)

 Supply supervisor for killing spikes during power on and off:

 threshold internally fixed

 externally by a resistor bridge (with SO28 package only)

2.2 Easy integration into your contact reader

 SW compatible to TDA8024, TDA8034 and TDA8035

 3 V smart card supply

 Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8)

 External clock input up to 20 MHz

 Card clock generation up to 20 MHz using pin CLKDIV with synchronous frequency

changes of fCLKIN, fCLKIN/2 (with SO28 package only)

 Non-inverted control of pin RST using pin RSTIN

 Built-in debouncing on card presence contact

 Multiplexed status signal using pin OFFN

 Chip Select digital input for parallel operation of several TDA8037 ICs (with SO28

package only)

NXP Semiconductors

7. Pinning information

7.1 Pinning

TDA8037

Low power 3V smart card interface

AUX1UC 1

AUX2UC 2

VDD 3

PRESN 4

I/O 5

AUX2 6

AUX1 7

GND 8

TDA8037TT

16 I/OUC

15 CLKIN

14 OFFN

13 RSTIN

12 CMDVCCN

11 VCC

10 RST

9 CLK

aaa-011373

Fig 2. Pin configuration TSSOP16

7.2 Pinning

CLKDIV 1

n.c. 2

n.c. 3

TEST 4

n.c. 5

VDD 6

n.c. 7

n.c. 8

PRESN 9

n.c. 10

I/O 11

AUX2 12

AUX1 13

GND 14

Fig 3. Pin configuration SO28

TDA8037T

28 AUX2UC

27 AUX1UC

26 I/OUC

25 n.c.

24 CLKIN

23 OFFN

22 n.c.

21 CS

20 RSTIN

19 CMDVCCN

18 PORADJ

17 VCC

16 RST

15 CLK

aaa-011374

TDA8037

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1.1 — 17 November 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

4 of 29

NXP Semiconductors

TDA8037

Low power 3V smart card interface

pulse of approximately 5.7 ms (tw = 2048  1/(fosc(int)_Low), is used internally for

maintaining the IC in an inactive mode during the supply voltage power-on (see Figure 5,

Figure 6, Figure 7, Figure 8 and Figure 9). When VDD falls below Vth(VDD), Vth(VREG) or

VDDhost falls below Vth(VDDhost), a deactivation sequence is performed.

Vth_VDD_LH

VDD

Vt

Vth_VDD_LH

Vth_VDD_HL

VSUP

(internal signal)

reset

(internal signal)

SUPALARM

(internal signal)

X

X

X

OFFN

X

Fig 5. Voltage supervisor

tw

tw

debouncing

tw

tw

debouncing

aaa-011376

8.3 Clock circuitry

To generate the card clock CLK, the TDA8037 uses an external clock provided on CLKIN

pin. Apply the external clock to CLKIN before CMDVCCN falling edge signal.

The frequency is chosen as fCLKIN, fCLKIN/2 via the pins CLKDIV.

The frequency change is synchronous, which means that during transition, no pulse is

shorter than 45 % of the smallest period. It ensures that the first and last clock pulse

around the change has the correct width. When changing the frequency dynamically, the

change is effective for only 10 periods of CLKIN after the command.

The duty cycle on pin CLK shall be between 45 % and 55 %.

Table 4.

CLKDIV

0

1

Clock configuration (SO28 only)

CLK

fCLKIN

fCLKIN/2

8.4 I/O circuitry

The three data lines I/O, AUX1 and AUX2 are identical.

By pulling both lines (I/O and I/OUC) HIGH via a 10 k resistor (I/O to VCC and I/OUC to

VDD), the idle state is realized.

I/O is referenced to VCC, and I/OUC to VDD, thus allowing operation with VCC  VDD.

TDA8037

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1.1 — 17 November 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

7 of 29

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