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Data Sheet

CDP1802AC/3

October 17, 2008

FN1441.3

High-Reliability CMOS 8-Bit

Microprocessor

The CDP1802A/3 High-Reliability LSI CMOS 8-bit register

oriented Central-Processing Unit (CPU) is designed for use

as a general purpose computing or control element in a wide

range of stored-program systems or products.

The CDP1802A/3 includes all of the circuits required for

fetching, interpreting, and executing instructions which have

been stored in standard types of memories. Extensive

input/output (I/O) control features are also provided to

facilitate system design.

The 1800 Series Architecture is designed with emphasis on

the total microcomputer system as an integral entity so that

systems having maximum flexibility and minimum cost can be

realized. The 1800 Series CPU also provides a synchronous

interface to memories and external controllers for I/O devices,

and minimizes the cost of interface controllers. Further, the I/O

interface is capable of supporting devices operating in polled,

interrupt-driven, or direct memory-access modes.

The CDP1802AC/3 is functionally identical to its

predecessor, the CDP1802. The “A” version includes some

performance enhancements and can be used as a direct

replacement in systems using the CDP1802.

This type is supplied in a 40 Ld dual-in-line sidebrazed

ceramic package (D suffix).

Features

For Use In Aerospace, Military, and Critical Industrial

Equipment

• Minimum Instruction Fetch-Execute Time of 4.5µs

(Maximum Clock Frequency of 3.6MHz) at VDD = 5V,

TA = +25°C

• Operation Over the Full Military

Temperature Range . . . . . . . . . . . . . . . -55°C to +125°C

• Any Combination of Standard RAM and ROM Up to

65,536 Bytes

• 8-Bit Parallel Organization With Bi-directional Data

Bus and Multiplexed Address Bus

• 16x16 Matrix of Registers for Use as Multiple Program

Counters, Data Pointers, or Data Registers

• On-Chip DMA, Interrupt, and Flag Inputs

• High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD

• Pb-Free (RoHS compliant)

Ordering Information

PART

NUMBER

PART

MARKING

TEMP. RANGE

(°C)

CLOCK FREQUENCY

AT 5V

PACKAGE

PKG

DWG. #

CDP1802ACD3

CDP1802ACD3

-55 to +125

Up to 3.2MHz

40 Ld SBDIP

D40.6

NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible

with both SnPb and Pb-free soldering operations.

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2002, 2008. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

CDP1802AC/3

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage Range, (VDD)

(All Voltages Referenced to VSS Terminal)

CDP1802AC/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V

DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . ±10mA

Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)

SBDIP Package . . . . . . . . . . . . . . . . . .

55

15

Device Dissipation Per Output Transistor

TA = Full Package Temperature Range . . . . . . . . . . . . . . .100mW

Operating Temperature Range (TA)

Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Storage Temperature Range (TSTG) . . . . . . . . . . . .-65°C to +150°C

Lead Temperature (During Soldering)

At distance 1/16 ± 1/32 In. (1.59 ±0.79mm)

from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Recommended Operating Conditions

TA = Full Package Temperature Range. For maximum reliability, operating conditions should

be selected so that operation is always within the following ranges. Parameters with MIN

and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits

established by characterization and are not production tested.

PARAMETER

MIN

MAX

UNITS

DC Operating Voltage Range

4 6.5 V

Input Voltage Range

Maximum Clock Input Rise or Fall Time

VSS

VDD

-1

V

µs

Performance Specifications Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.

Temperature limits established by characterization and are not production tested.

PARAMETER

VDD

(V)

-55°C TO +25°C

+125°C

UNITS

Minimum Instruction Time (Note 3)

5 4.5 5.9 µs

Maximum DMA Transfer Rate

5 450 340 Kbytes/s

Maximum Clock Input Frequency,

Load Capacitance (CL) = 50pF, fCL

5

DC-3.6

DC-2.7

MHz

NOTE:

3. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3 machine

cycles - one Fetch and two Execute operations.

Static Electrical Specifications All Limits are 100% Tested. Parameters with MIN and/or MAX limits are 100% tested at +25°C,

unless otherwise specified. Temperature limits established by characterization and are not

production tested.

CONDITIONS

-55°C, +25°C

+125°C

PARAMETER

VOUT

(V)

VIN,

(V)

VCC, VDD

(V)

(Note 4)

MIN MAX MIN MAX UNITS

Quiescent Device Current, IDD

Output Low Drive (Sink) Current

(Except XTAL), IOL

XTAL

--

0.4 0, 5

0.4 5

5 - 100 - 250 µA

5 1.20 - 0.90 - mA

5 185 - 140 - µA

Output High Drive (Source)

Current (Except XTAL), IOH

XTAL

4.6 0, 5

4.6 0

5

5

- -0.30

-

-0.20

mA

- -135

-

-100

µA

Output Voltage Low-Level, VOL

- 0, 5

5

- 0.1 - 0.2 V

4 FN1441.3

October 17, 2008

CDP1802AC/3

Timing Waveforms

CLOCK

ADDRESS

FETCH (READ)

EXECUTE (WRITE)

00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00

HI BYTE

LOW BYTE

HI BYTE

LOW BYTE

TPA

TPB

MRD

MWR

DATA

VALID INPUT DATA

VALID OUTPUT DATA

FIGURE 1. BASIC DC TIMING WAVEFORM, ONE INSTRUCTION CYCLE

7 FN1441.3

October 17, 2008

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