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ASAHI KASEI

[AK4536]

AK4536

16-Bit Mono CODEC with ALC & MIC/SPK-AMP

GENERAL DESCRIPTION

The AK4536 is a 16-bit mono CODEC with Microphone-Amplifier and Speaker-Amplifier. Input circuits

include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a

Speaker-Amplifier and Mono Line Output. The AK4536 suits a moving picture of Digital Still Camera and

etc. The AK4536 is housed in a space-saving 28-pin QFN package.

FEATURE

1. 16-Bit Delta-Sigma Mono CODEC

2. Recording Function

• 1ch Mono Input

• 1st MIC Amplifier: 0dB or 20dB

• 2nd Amplifier with ALC: -8dB ∼ +27.5dB, 0.5dB Step

• ADC Performance: S/(N+D): 80dB, DR, S/N: 85dB

3. Playback Function

• Digital Volume: +12dB ∼ -115dB, 0.5dB Step, Mute

• Mono Line Output Performance: S/(N+D): 85dB, S/N: 95dB

• Mono Speaker-Amp

- Speaker-Amp Performance: S/(N+D): 50dB, S/N: 90dB (Po = 250mW)

- BTL Output

- ALC (Automatic Level Control) Circuit

- Output Power: 250mW @ 8Ω, SVDD=3.3V

• Beep Input

4. Power Management

5. Flexible PLL Mode:

• Frequencies: 11.2896MHz, 12MHz or 12.288MHz (MCKI pin)

1fs (FCK pin)

16fs, 32fs or 64fs (BICK pin)

• Input Level: CMOS or AC Coupling (MCKI pin)

6. EXT Mode:

• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)

• Input Level: CMOS or AC Coupling (MCKI pin)

7. Sampling Rate:

• PLL Slave Mode: 7.35kHz ∼ 26kHz

• PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz or 24kHz

• EXT Slave Mode: 7.35kHz ∼ 26kHz (256fs or 512fs), 7.35kHz ∼ 13kHz (1024fs)

8. Serial µP Interface: 3-wire

9. Master / Slave Mode

10. Audio Interface Format: MSB First, 2’s compliment

• ADC: DSP Mode, 16bit MSB justified, I2S

• DAC: DSP Mode, 16bit MSB justified, 16bit LSB justified, I2S

11. Ta = -10 ∼ 70°C

12. Power Supply

• CODEC, Speaker-Amp: 2.4 ∼ 3.6V (typ. 3.3V)

13. Power Supply Current: 19mA (All Power ON)

14. Package: 28pin QFN

MS0174-E-00

-1-

2002/09

ASAHI KASEI

[AK4536]

PIN/FUNCTION

No. Pin Name

1 VCOM

2 AVSS

3 AVDD

4 VCOC

5 PDN

6 CSN

7 CCLK

8 CDTI

9 SDTI

10 SDTO

11 FCK

12 BICK

13 DVDD

14 DVSS

XTI

15

MCKI

16 XTO

17 SPP

18 SPN

19 SVDD

20 SVSS

21 MIN

22 MOUT

23 AOUT

24 BEEP

25 AIN

26 MICOUT

27 MIC

28 MPI

I/O Function

Common Voltage Output Pin, 0.45 x AVDD

O

Bias voltage of ADC inputs and DAC outputs.

- Analog Ground Pin

- Analog Power Supply Pin

Output Pin for Loop Filter of PLL Circuit

O

This pin should be connected to AVSS with one resistor and capacitor in series.

Power-Down Mode Pin

I

“H”: Power up, “L”: Power down reset and initialize the control register.

I Chip Select Pin

I Control Data Clock Pin

I Control Data Input Pin

I Audio Serial Data Input Pin

O Audio Serial Data Output Pin

I/O Frame Clock Pin

I/O Audio Serial Data Clock Pin

- Digital Power Supply Pin

- Digital Ground Pin

I X’tal Input Pin

I External Master Clock Input Pin

O X’tal Output Pin

O Speaker Amp Positive Output Pin

O Speaker Amp Negative Output Pin

- Speaker Amp Power Supply Pin

- Speaker Amp Ground Pin

I ALC2 Input Pin

O Mono Analog Output Pin

O Mono Line Output Pin

I Beep Signal Input Pin

I IPGA (ALC1) Input Pin

O Microphone Analog Output Pin

I Microphone Input Pin (Mono Input)

O MIC Power Supply Pin for Microphone

Note: All input pins except analog input pins (MIC, AIN, MIN and BEEP pins) should not be left floating.

MS0174-E-00

-4-

2002/09

ASAHI KASEI

[AK4536]

Parameter

min typ max Units

Power Supplies

Power Up (PDN = “H”)

All Circuit Power-up: (Note 16)

AVDD+DVDD

10 15 mA

SVDD: Speaker-Amp Normal Operation

(SPPS bit = “1”, No Output)

9 18 mA

Power Down (PDN = “L”) (Note 17)

AVDD+DVDD+SVDD

10 200 µA

Note 4. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ)

Note 5. When IPGA Gain is changed, this typical value changes between 8kΩ and 11kΩ.

Note 6. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)

Note 7. When a PLL reference clock is FCK pin in PLL Slave Mode, S/(N+D) is 60dB (typ).

Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)

Note 9. Input signal of MIN pin is 1.98Vpp.

Note 10. There are no relations with the setup of SPKG bit, and it is the same value.

Note 11. The maximum input voltage of the BEEP input shows output from AOUT.

Note 12. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.66 x AVDD (max)

Note 13. When ALC2 Gain is changed, this typical value changes between 22kΩ and 26kΩ.

Note 14. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)

Note 15. When the output pin drives a capacitive load, a resistor should be added in series between the output pin and

capacitive load.

Note 16. PLL Master Mode (X’tal = 12.288MHz) and PMMIC = PMADC = PMDAC = PMSPK = PMVCM = PMPLL =

PMXTL = PMAO = PMBP = M/S = “1”. And output current from MPI pin is 0mA. When the AK4536 is EXT

mode (PMPLL = PMXTL = M/S = “0”), “AVDD+DVDD” is typically 8mA.

Note 17. All digital input pins are fixed to DVDD or DVSS.

MS0174-E-00

-7-

2002/09

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