PDF MST9883 Data sheet ( Hoja de datos )

Número de pieza	MST9883
Descripción	Triple Video A/D Converter
Fabricantes	Mstar
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No Preview Available ! MST9883 110 MSPS/140 MSPS Triple Video A/D Converter with Clamps & Pixel Clock Synthesizer FEATURES OVERVIEW u Triple ADC with 12 - 140 MHz Sampling Rate u Integrated line locked PLL generates pixel clock from HSYNC u Integrated 5-bit pixel clock phase adjustment for precise sample timing control u Integrated clamp with timing generator u Integrated Brightness & Contrast controls u Integrated precision voltage reference u Compatible with VGA through SXGA RGB graphics signals u Pin Compatible with AD9883A u Serial port programming interface u Mid-Scale Clamping u Fully Sync Processing u 4:2:2 Output Format Mode BLOCK DIAGRAM DESCRIPTION Most flat-panel monitors and projectors require a digital graphics input in order to accurately scale and display graphics. The huge installed base of computers with analog video graphics interfaces necessitates the use of a graphics digitizer to re-digitize the analog RGB signal before further processing. u The MST9883 is a fully integrated analog interface for digitizing high-resolution RGB graphics signals from PC’s and workstations. With a sampling rate capability of up to 140 MHz, it can accurately support display resolutions up to 1280x1024 (SXGA) at 75 Hz. The clamped input circuits provide sufficient bandwidth to accurately digitize each pixel. u The MST9883 provides a high performance highly integrated solution to support the digitization process, including the ADC’s, a voltage reference, a PLL to generate the pixel sampling clock from HSYNC, clamping circuits, and programmable offset and gain circuits to provide brightness and contrast controls. u When the COAST signal is asserted, the PLL will maintain its output frequency when HSYNC pulses are absent, such as during the VSYNC period in some systems. u A 32-step programmable phase adjustment control (0-360 deg) is provided for the pixel sampling clock to adjust for the difference between the HSYNC edge and RGB pixel edge timing. u The MST9883 can send output data through one 24-bit port at the pixel clock rate. Version 1.6 -1- Copyright © 2003 MStar Semiconductor, Inc. All rights reserved. Confidential information 3/7/2003 1 page REGISTER NAME SYNCTRL Register Bit Alias 7 HPO Value 0 1 0 6 HSPOL 1 5 HSOUTPOL 0 1 4 AHO 0 1 3 AHS 0 1 2 VOI 0 1 1 AVO 0 1 0 AVS 0 1 MST9883 110 MSPS/140 MSPS Triple Video A/D Converter with Clamps & Pixel Clock Synthesizer SUB-ADDRESS 0EH (R/W) Function HSYNC polarity determined by chip (default) HSYNC polarity determined by user HSYNC treated as active low. PLL will synchronize to falling (leading) edge of HSYNC input, and clamp will synchronize to rising (trailing) edge of HSYNC. HSYNC treated as active high. PLL will synchronize to rising (leading) edge of HSYNC input, and clamp will synchronize to falling (trailing) edge of HSYNC. (default) Positive output signal polarity for HSOUT & SOGOUT (default) Negative output signal polarity for HSOUT & SOGOUT Auto determines the Active Interface (default) Override, AHS (Bit 3) determines the Active Interface HSYNC Input (default) Sync-On-Green Input Inverts the output polarity of VSYNC Not inverts the output polarity of VSYNC (default) Auto determines the Active VSYNC (default) Override, AVS (Bit 0) determines the Active VSYNC VSYNC Input (default) Sync Separator Output Version 1.6 -5- Copyright © 2003 MStar Semiconductor, Inc. All rights reserved. Confidential information 3/7/2003 5 Page MST9883 110 MSPS/140 MSPS Triple Video A/D Converter with Clamps & Pixel Clock Synthesizer Specifications are subjected to change without notice. Explanation of Test Levels Test Level 1. 100% production tested 2. Parameter is guaranteed by design and characterization testing 3. Parameter is a typical value only 4. 100% production tested at 25°C; guaranteed by design and characterization testing 2-WIRE SERIAL BUS SPECIFICATION Parameter Symbol Hold time (repeated) START condition. After this period, the first clock pulse is generated tHD;STA LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time: Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF ABSOLUTE MAXIMUM RATINGS♠ STANDARD-MODE Min 4.0 4.7 4.0 4.7 0 250 - - 4.0 4.7 Max - - - - 3.45 - 1000 300 - - Unit µs µs µs µs µs ns ns ns µs µs Parameter AVDD, PVDD VDD Analog Inputs VREF Digital Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature Rating -0.5 ~ +3.6 -0.5 ~ +3.6 -0.5 ~ AVDD 0.0 ~ AVDD 0.0 ~ 5.0 20 -20 ~ +80 -65 ~ +150 +150 +150 Units V V V V V mA ºC ºC ºC ºC ♠ Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside of the limits indicated in this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Version 1.6 - 11 - Copyright © 2003 MStar Semiconductor, Inc. All rights reserved. 3/7/2003 11 Page

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