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Descripción Express Chipset
Fabricantes Intel　
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Intel® G31/P31 Express Chipset
Datasheet
— For the Intel® 82G31 Graphics and Memory Controller Hub
(GMCH) and the Intel® 82P31 Memory Controller Hub (MCH)
July 2007
Document Number: 317495-001

1 page




82P31 pdf
5.1.18 PAM0—Programmable Attribute Map 0........................................89
5.1.19 PAM1—Programmable Attribute Map 1........................................91
5.1.20 PAM2—Programmable Attribute Map 2........................................92
5.1.21 PAM3—Programmable Attribute Map 3........................................93
5.1.22 PAM4—Programmable Attribute Map 4........................................94
5.1.23 PAM5—Programmable Attribute Map 5........................................95
5.1.24 PAM6—Programmable Attribute Map 6........................................96
5.1.25 LAC—Legacy Access Control......................................................97
5.1.26 REMAPBASE—Remap Base Address Register................................ 98
5.1.27 REMAPLIMIT—Remap Limit Address Register ...............................98
5.1.28 SMRAM—System Management RAM Control ................................99
5.1.29 ESMRAMC—Extended System Management RAM Control ............. 100
5.1.30 TOM—Top of Memory............................................................. 101
5.1.31 TOUUD—Top of Upper Usable Dram ......................................... 102
5.1.32 GBSM—Graphics Base of Stolen Memory................................... 103
5.1.33 BGSM—Base of GTT stolen Memory.......................................... 104
5.1.34 TSEGMB—TSEG Memory Base ................................................. 104
5.1.35 TOLUD—Top of Low Usable DRAM ............................................ 105
5.1.36 ERRSTS—Error Status ............................................................ 106
5.1.37 ERRCMD—Error Command ...................................................... 108
5.1.38 SMICMD—SMI Command........................................................ 109
5.1.39 SKPD—Scratchpad Data ......................................................... 109
5.1.40 CAPID0—Capability Identifier .................................................. 110
5.2 MCHBAR ........................................................................................... 114
5.2.1 CHDECMISC—Channel Decode Miscellaneous............................. 116
5.2.2 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 ................. 117
5.2.3 C0CYCTRKPCHG—Channel 0 CYCTRK PCHG............................... 118
5.2.4 C0CYCTRKACT—Channel 0 CYCTRK ACT ................................... 119
5.2.5 C0CYCTRKWR—Channel 0 CYCTRK WR ..................................... 120
5.2.6 C0CYCTRKRD—Channel 0 CYCTRK READ................................... 121
5.2.7 C0CYCTRKREFR—Channel 0 CYCTRK REFR ................................ 121
5.2.8 C0CKECTRL—Channel 0 CKE Control ........................................ 122
5.2.9 C0REFRCTRL—Channel 0 DRAM Refresh Control......................... 123
5.2.10 C0ODTCTRL—Channel 0 ODT Control ....................................... 124
5.2.11 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 ................. 125
5.2.12 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 ................. 125
5.2.13 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 ................. 126
5.2.14 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 ................. 126
5.2.15 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes ........................ 127
5.2.16 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes ........................ 127
5.2.17 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG............................... 128
5.2.18 C1CYCTRKACT—Channel 1 CYCTRK ACT ................................... 129
5.2.19 C1CYCTRKWR—Channel 1 CYCTRK WR ..................................... 130
5.2.20 C1CYCTRKRD—Channel 1 CYCTRK READ................................... 131
5.2.21 C1CKECTRL—Channel 1 CKE Control ........................................ 132
5.2.22 C1REFRCTRL—Channel 1 DRAM Refresh Control......................... 133
5.2.23 C1ODTCTRL—Channel 1 ODT Control ....................................... 135
5.2.24 EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1 ......... 136
5.2.25 EPC0DRB2—EP Channel 0 DRAM Rank Boundary Address 2 ......... 136
5.2.26 EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3 ......... 136
5.2.27 EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute.................. 137
5.2.28 EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute.................. 137
5.2.29 EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE............................. 138
5.2.30 EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT ............................ 138
5.2.31 EPDCYCTRKWRTWR—EPD CYCTRK WRT WR .............................. 139
Datasheet
5

5 Page





82P31 arduino
Tables
Table 3-1. Expansion Area Memory Segments .....................................................46
Table 3-2. Extended System BIOS Area Memory Segments ...................................47
Table 3-3. System BIOS Area Memory Segments.................................................47
Table 3-4. Pre-allocated Memory Example for 64 MB DRAM, 1 MB VGA, 1 MB
GTT stolen and 1 MB TSEG ................................................................49
Table 3-5. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and
1-MB TSEG......................................................................................56
Table 3-6. SMM Space Table.............................................................................57
Table 5-1. DRAM Controller Register Address Map (D0:F0)....................................73
Table 5-2. MCHBAR Register Address Map ........................................................ 114
Table 5-3. EPBAR Register Address Map ........................................................... 156
Table 6-1. PCI Express* Register Address Map (Device 1, Function 0)................... 161
Table 7-1. DMI Register Address Map............................................................... 213
Table 8-1. Integrated Graphics Device Register Address Map
(Device 2, Function 0) .................................................................... 223
Table 8-2. Integrated Graphics Device Register Address Map (D2:F1) ................... 246
Table 9-1. Sample System Memory Dual Channel Symmetric Organization
Mode with Intel® Flex Memory Mode Enabled..................................... 269
Table 9-2. Sample System Memory Dual Channel Asymmetric Organization
Mode with Intel® Flex Memory Mode Disabled .................................... 269
Table 9-3. Supported DIMM Module Configurations ............................................ 270
Table 9-4. Concurrent sDVO / PCI Express* Configuration Strap Controls.............. 274
Table 10-1. Absolute Minimum and Maximum Ratings ........................................ 287
Table 10-2. Current Consumption in S0........................................................... 289
Table 10-4. Signal Groups .............................................................................. 291
Table 10-5. I/O Buffer Supply Voltage............................................................. 295
Table 10-6. DC Characteristics ....................................................................... 296
Table 10-7. R, G, B / CRT DAC Display DC Characteristics: Functional
Operating Range (VCCA_DAC = 3.3 V ± 5%) .................................... 300
Table 11-1. (G)MCH Ballout Sorted by Signal Name ........................................... 305
Table 12-1. XOR Chain 14 functionality ............................................................ 318
Table 12-2. XOR Chain Outputs....................................................................... 319
Table 12-3. XOR Chain 0................................................................................ 320
Table 12-4. XOR Chain 1................................................................................ 321
Table 12-5. XOR Chain 2................................................................................ 321
Table 12-6. XOR Chain 3................................................................................ 322
Table 12-7. XOR Chain 4................................................................................ 322
Table 12-8. XOR Chain 5................................................................................ 322
Table 12-9. XOR Chain 6................................................................................ 323
Table 12-10. XOR Chain 8 .............................................................................. 324
Table 12-11. XOR Chain 9 .............................................................................. 325
Table 12-12. XOR Chain 10 ............................................................................ 325
Table 12-13. XOR Chain 12 ............................................................................ 326
Table 12-14. XOR Chain 13 ............................................................................ 326
Table 12-15. XOR Chain 14 ............................................................................ 326
Datasheet
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