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부품번호 | ET1815 기능 |
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기능 | Slave Controller IP Core | ||
제조업체 | Beckhoff | ||
로고 | |||
Hardware Data Sheet
ET1815 / ET1817
Slave Controller IP Core
for Xilinx FPGAs
IP Core Release 2.02a
Section I –
EtherCAT Slave Controller Technology
Section II –
EtherCAT Slave Controller Register Description
Section III –
EtherCAT IP Core Description: Installation, Configuration,
Design flow, Interface specification
Version 2.2.1
Date: 2008-09-01
DOCUMENT ORGANIZATION
DOCUMENT ORGANIZATION
The Beckhoff EtherCAT Slave Controller (ESC) documentation covers the following Beckhoff ESCs:
• ET1200
• ET1100
• EtherCAT IP Core for Altera FPGAs
• EtherCAT IP Core for Xilinx FPGAs
• ESC20
The documentation is organized in three sections. Section I and section II are common for all Beckhoff
ESCs, Section III is specific for each ESC variant.
Section I – Technology (All ESCs)
Section I deals with the basic EtherCAT technology. Starting with the EtherCAT protocol itself, the
frame processing inside EtherCAT slaves is described. The features and interfaces of the physical
layer with its two alternatives Ethernet and EBUS are explained afterwards. Finally, the details of the
functional units of an ESC like FMMU, SyncManager, Distributed Clocks, Slave Information Interface,
Interrupts, Watchdogs, and so on, are described.
Since Section I is common for all Beckhoff ESCs, it might describe features which are not available in
a specific ESC. Refer to the feature details overview in Section III of a specific ESC to find out which
features are available.
Section II – Register Description (All ESCs)
Section II contains detailed information about all ESC registers. This section is also common for all
Beckhoff ESCs, thus registers, register bits, or features are described which might not be available in
a specific ESC. Refer to the register overview and to the feature details overview in Section III of a
specific ESC to find out which registers and features are available.
Section III – Hardware Description (Specific ESC)
Section III is ESC specific and contains detailed information about the ESC features, implemented
registers, configuration, interfaces, pinout, usage, electrical and mechanical specification, and so on.
Especially the Process Data Interfaces (PDI) supported by the ESC are part of this section.
Additional Documentation
Additional documentation and utilities like application notes and Excel sheets for ET1100/ET1200
pinout configuration can be found at the Beckhoff homepage (http://www.beckhoff.com –
Download/Documentation/EtherCAT development products).
C-IV
Slave Controller – IP Core for Xilinx FPGAs
4페이지 DOCUMENT HISTORY
Version
1.0
1.1
1.2
1.2.1
1.3
1.4
DOCUMENT HISTORY
Comment
Initial release
• Chapter Interrupts – AL Event Request: corrected AL Event Mask register
address to 0x0204:0x0207
• EtherCAT Datagram: Circulating Frame bit has position 14 (not 13)
• PHY addressing configuration changed
• Loop control: a port using Auto close mode is automatically opened if a valid
Ethernet frame is received at this port
• EEPROM read/write/reload example: steps 1 and 2 swapped
• EEPROM: Configured Station Alias (0x0012:0x0013) is only taken over at first
EEPROM load after power-on or reset
• SyncManager: Watchdog trigger and interrupt generation in mailbox mode with
single byte buffers requires alternating write and read accesses for some ESCs,
thus buffered mode is required for Digital I/O watchdog trigger generation
• National Semiconductor DP83849I Ethernet PHY deprecated because of large
link loss reaction time and delay
• Added distinction between permanent ports and Bridge port (frame processing)
• Added PDI chapter
• PDI and DC Sync/Latch signals are high impedance until the ESI EEPROM is
successfully loaded
• Editorial changes
• PHY address configuration revised. Refer to Section III for ESC supported
configurations
• Added Ethernet Link detection chapter
• Added MI Link Detection and Configuration, link detection descriptions updated
• Added EEPROM Emulation for EtherCAT IP Core
• Added General Purpose Input chapter
• Corrected minimum datagram sizes in EtherCAT header figure
• Editorial changes
• Chapter 5.1.1: incompatible PHYs in footnote 1 deleted
• Added advisory for unused MII/RMII/EBUS ports
• Ethernet PHY requirements revised: e.g., configuration by strapping options,
recommendations enhanced. Footnote about compatible PHYs removed,
information has moved to the EtherCAT Slave Controller application note “PHY
Selection Guide”.
• Frame Error detection chapter enhanced
• FIFO size reduction chapter enhanced
• EBUS enhanced link detection chapter enhanced
• Ethernet PHY link loss reaction time must be faster than 15 µs, otherwise use
Enhanced link detection
• Enhanced link detection description corrected. Enhanced link detection does
not remain active if it is disabled by EEPROM and EBUS handshake frames are
received
• ARMW/FRWM commands increase the working counter by 1
• Editorial changes
• Update to EtherCAT IP Core Release 2.1.0/2.01a
• Added restriction to enhanced link configuration: RX_ER has to be asserted
outside of frames (IEEE802 optional feature)
• ESC power-on sequence for IP Core corrected
• Removed footnote on tDiff figures, refer to Section III for actual figures
• Editorial changes
Slave Controller – Technology
I-III
7페이지 | |||
구 성 | 총 30 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
ET1815 | Slave Controller IP Core | Beckhoff |
ET1817 | Slave Controller IP Core | Beckhoff |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |