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PDF NT68563EF Data sheet ( Hoja de datos )

Número de pieza NT68563EF
Descripción Flat Panel Monitor Controller
Fabricantes Novatek　
Logotipo Novatek Logotipo



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No Preview Available ! NT68563EF Hoja de datos, Descripción, Manual

For NT68563XF/NT68563EF
Flat Panel Monitor Controller
Preliminary
Draft. 0.95
2005-01-20

1 page




NT68563EF pdf
NT68563
Flat Panel Monitor Controller
2. FEATURES
Analog Graphic Input
 Integrated triple high speed ADC/PLL
 0.55V to 0.9V Analog input range
 Supports both non-interlaced and interlaced input signals.
 Supports Analog YPbPr input signals clamping, the signals are slightly different from RGB signal
in that the dc reference level
 64 steps of phase adjust for each RGB channel
 Sampling rate up to 110MHz for X type, 165MHz for E type.
 500 MHz programmable analog bandwidth
 Alternate sampling technology for higher input resolution up to UXGA
Digital Graphic Input
 Integrated single link DVI receiver
 Direct connect to all DVI compliant TMDS transmitters
 Operating up to up to 110MHz for X type (XGA), 165MHz for E type (SXGA)
Digital Video Input
 Supports ITU-R BT.656 8-bit Input format
 Built-in YUV to RGB color space converter
 Spatial de-interlace
Display Output
 Supports single pixel or dual pixel output
 Spread spectrum clock (SSC) output, output signals drive current and slew rate control for low
EMI
 Dithering function supports 24-bit quality for 18-bit panel
 Optional Frame Sync or Free Run display synchronization modes
 10-bit programmable gamma correction
 2 channel PWM output for LCD back-light control or volume control
 Display resolution up to SXGA
 Supports sRGB input
Built-in Dual Pixel LVDS Transmitter
 Integrate the Dual Port, 4 Data Channel and Clock-Out Low-Voltage differential LVDS transmitter
to supports single or dual pixel 6/8-bit display data transmission.
 Suited for VGA, SVGA, XGA and dual pixel SXGA, UXGA display transmission from controller to
display with very low EMI
Video Processing
 Independent horizontal and vertical zoom and shrink
 Auto-calibration function for quick video positioning, clock tracking and phase adjust
 Programmable H-sync pulse guard window prevent the position detecting error
 Enhancement Back-end brightness, contrast, Hue, Saturation and sharpness adjust
 Built-in adaptive Noise Reduction function
 Built-in Post Pattern generator
 Support Bright Frame function
2005-01-26
5
Ver. 0.95

5 Page





NT68563EF arduino
35 RIN0+
36 RIN0-
37 NC/ADC_GNDA
38 VREF
39 HSYNCI1
40 VSYNCI1
TOUTP
41 HSYNCI0
42 VSYNCI0
43 PLL_ GND
44 OSCO
45 OSCI
46 PLL_ VDD
47 PWM0/GPO10
48 PWM1/GPO9
49~50 GPO [8:7] / AD [2:3]
51 YUV_CLK
52 DGND
53 CVDD
54 DVDD
55~62 Y [0:7]
63 DGND
64~71 NC
72 DVDD
73 T7P
74 T7M
75 TCLK2P
76 TCLK2M
77 T6P
78 T6M
79 T5P
80 T5M
81 T4P
82 T4M
NT68563
Flat Panel Monitor Controller
I
I
Power
I
I
I
O
I
I
Power
I/O
I
Power
I/O
I/O
TTL O
I
Power
Power
Power
I
Power
R channel positive analog video input
R channel negative analog video input
ADC analog ground
External reference voltage (2.5V)
VGA Port Channel1Horizontal Sync Input with Schmitt
trigger, when HPLL is enabling.
VGA Port Channel 1Vertical Sync Input with Schmitt trigger
Testing pin for ADC
VGA Port Channel 0 Horizontal Sync Input with Schmitt
trigger, when HPLL is enabling.
VGA Port Channel 0Vertical Sync Input with Schmitt trigger
Core Logic Ground pin for PLL.
Crystal OSC Output
Crystal OSC Input
Core logic power supply (1.8V) pin for PLL. External
capacitor (0.1uF) connected is recommended.
PWM0/ General purpose output
PWM1/ General purpose output
General purpose output for panel driver / Parallel 4-Bits
Bus address and data bus
Video Port Clock
Digital Ground/ Core Logic Ground
Core logic power supply (1.8V) pin. External capacitor
(0.1uF) connected is recommended.
Display Digital Power Supply
Y Video Data [0:7] Input
Digital Ground/ Core Logic Ground
Power Display Digital Power Supply
LVDSO Positive LVDS differential data output of channel 7
LVDSO Negative LVDS differential data output of channel 7
LVDSO Positive LVDS differential clock 2 output
LVDSO Negative LVDS differential clock 2 output
LVDSO Positive LVDS differential data output of channel 6
LVDSO Negative LVDS differential data output of channel 6
LVDSO Positive LVDS differential data output of channel 5
LVDSO Negative LVDS differential data output of channel 5
LVDSO Positive LVDS differential data output of channel 4
LVDSO Negative LVDS differential data output of channel 4
2005-01-26
11
Ver. 0.95

11 Page







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