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PDF CHY100 Data sheet ( Hoja de datos )
| Número de pieza | CHY100 | |
| Descripción | Charger Interface Physical Layer IC | |
| Fabricantes | Power Integrations | |
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Hay una vista previa y un enlace de descarga de CHY100 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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CHY100
ChiPhy™ Family
Charger Interface Physical Layer IC
Product Highlights
• Fully supports Quick Charge 2.0 specification
• Class A: 5 V, 9 V, and 12 V output voltage
• Class B: 5 V, 9 V, 12 V, and 20 V output voltage
• USB battery charging specification revision 1.2 compatible
• Automatic USB DCP shorting D+ to D- line
• Default 5 V mode operation
• Supports TOPSwitch and TinySwitch
• Very low power consumption
• Below 1 mW at 5 V output
• Fail safe operation
• Adjacent pin-to-pin short-circuit fault
• Open circuit pin fault
Typical Applications
• Battery chargers for smart phones, tablets, netbooks, digital
cameras, and bluetooth accessories
• USB power output ports
Description
CHY100 is a low-cost USB high-voltage dedicated charging port
(HVDCP) interface IC for the Quick Charge 2.0 specification. It
incorporates all necessary functions to add Quick Charge 2.0
capability to Power Integrations’ switcher ICs such as TOPSwitch
or TinySwitch and other solutions employing traditional feedback
schemes.
CHY100 supports the full output voltage range of either Class A
or Class B. Optionally Class B can be inhibited for protecting the
battery charger from accidental damage.
CHY100 automatically detects whether a connected Powered
Device (PD) is Quick Charge 2.0 capable before enabling output
voltage adjustment. If a PD not compliant to Quick Charge 2.0 is
detected the CHY100 disables output voltage adjustment to
ensure safe operation with legacy 5 V only USB PDs.
VOUT
D+
D-
GND
Feedback
Network
BP
V3 D+
V2 CHY100 D-
U1
V1 R
GND
Figure 1. Typical Application Schematic.
PI-6988-071713
Figure 2. Package Option.
SO-8 (D Package)
www.powerint.com
This Product is Covered by Patents and/or Pending Patent Applications.
March 2014
1 page  
CHY100
SO-8 (D Package)
4B
2
4.90 (0.193) BSC
0.10 (0.004) C A-B 2X
A
8
4
D
5
2 3.90 (0.154) BSC
0.10 (0.004) C D
2X Pin 1 ID
1.27 (0.050) BSC
1
1.35 (0.053)
1.75 (0.069)
0.10 (0.004)
0.25 (0.010)
1.25 - 1.65
(0.049 - 0.065)
6.00 (0.236) BSC
SEATING
PLANE
C
1.04 (0.041) REF
4 0.20 (0.008) C
2X
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D
0.40 (0.016)
1.27 (0.050)
0.10 (0.004) C
7X
SEATING PLANE
C
H
0.17 (0.007)
0.25 (0.010)
DETAIL A
GAUGE
PLANE
0 - 8o
0.25 (0.010)
BSC
DETAIL A
Reference
Solder Pad
Dimensions
+
1.45 (0.057) 4.00 (0.157) 5.45 (0.215)
D08A
1.27 (0.050)
++
+
0.60 (0.024)
Notes:
1. JEDEC reference: MS-012.
2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
PI-5615-041210
Part Ordering Information
CHY 100 D
www.powerint.com
• ChiPhy Product Family
• 100 Series Number
• Package Identifier
D SO-8
5
Rev. C 03/14
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CHY100.PDF ] | |
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