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PDF K4T1G084QG Data sheet ( Hoja de datos )
| Número de pieza | K4T1G084QG | |
| Descripción | 1Gb G-die DDR2 SDRAM | |
| Fabricantes | Samsung semiconductor | |
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Rev. 1.0, Feb. 2014
K4T1G084QG
K4T1G164QG
1Gb G-die DDR2 SDRAM Industrial
60FBGA/84FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2014 Samsung Electronics Co., Ltd. All rights reserved.
-1-
1 page  
K4T1G084QG
K4T1G164QG
datasheet
Rev. 1.0
Industrial DDR2 SDRAM
3. Package pinout/Mechanical Dimension & Addressing
3.1 x8 Package Pinout (Top view) : 60ball FBGA Package
1 2 3 456 7 8 9
A
VDD NU/RDQS
VSS
B DQ6 VSSQ DM/RDQS
C VDDQ DQ1 VDDQ
D DQ4 VSSQ DQ3
E
VDD
VREF
VSS
F
CKE
WE
G BA2 BA0 BA1
H
A10/AP
A1
J VSS
A3
A5
K A7 A9
L VDD A12
NC
VSSQ
DQS
VDDQ
DQ2
VSS
RAS
CAS
A2
A6
A11
NC
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT0
VDD
VSS
NOTE :
1. Pins B3 and A2 have identical capacitances as pins B7 and A8.
2. For a Read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair
DQS & DQS and input data masking function is disabled.
3. The function of DM or RDQS/RDQS is enabled by EMRS command.
Ball Locations (x8)
Populated ball
Ball not populated
Top view
(See the balls through package)
123456789
A
B
C
D
E
F
G
H
J
K
L
-5-
5 Page 
K4T1G084QG
K4T1G164QG
datasheet
Rev. 1.0
Industrial DDR2 SDRAM
6. Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
NOTE
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
V1
V1
V1
V1
C 1, 2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ. When VDD and VDDQ and VDDL are less than 500mV, VREF
may be equal to or less than 300mV.
4. Voltage on any input or I/O may not exceed voltage on VDDQ.
7. AC & DC Operating Conditions
7.1 Recommended DC operating Conditions (SSTL_1.8)
Symbol
Parameter
Min.
Rating
Typ.
Max.
Units
NOTE
VDD Supply Voltage
1.7 1.8 1.9 V
VDDL
Supply Voltage for DLL
1.7 1.8 1.9 V 4
VDDQ
Supply Voltage for Output
1.7 1.8 1.9 V 4
VREF
Input Reference Voltage
0.49*VDDQ
0.50*VDDQ
0.51*VDDQ
mV
1,2
VTT Termination Voltage
VREF-0.04
VREF
VREF+0.04
V
3
NOTE :There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting
device and VREF is expected to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
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