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기능 1Gb G-die DDR2 SDRAM
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K4T1G164QG 데이터시트, 핀배열, 회로
Rev. 1.0, Feb. 2014
K4T1G084QG
K4T1G164QG
1Gb G-die DDR2 SDRAM Industrial
60FBGA/84FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2014 Samsung Electronics Co., Ltd. All rights reserved.
-1-




K4T1G164QG pdf, 반도체, 판매, 대치품
K4T1G084QG
K4T1G164QG
datasheet
1. Ordering Information
Organization
128Mx8
64Mx16
DDR2-800 (5-5-5)
K4T1G084QG-BI(P)E7
K4T1G164QG-BI(P)E7
DDR2-800 (6-6-6)
K4T1G084QG-BI(P)F7
K4T1G164QG-BI(P)F7
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. RoHS Compliant.
3. “B” of Part number(12th digit) stands for flip chip FBGA PKG.
4. “I” of Part number(13th digit) stands normal, and “P” stands for Low power products.
Rev. 1.0
Industrial DDR2 SDRAM
DDR2-667 (5-5-5)
K4T1G084QG-BI(P)E6
K4T1G164QG-BI(P)E6
Package
60 FBGA
84 FBGA
2. Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-800 5-5-5
5
12.5
12.5
57.5
DDR2-800 6-6-6
6
15
15
60
DDR2-667 5-5-5
5
15
15
60
Units
tCK
ns
ns
ns
• JEDEC standard VDD = 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latenc y: 0, 1, 2, 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is
an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
- 50ohm ODT
- High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at -40C < TCASE < 95 C
• All of products are Lead-Free, Halogen-Free, and RoHS compliant
The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x 8banks, 8Mbit
x 16 I/Os x 8 banks device. This synchronous device achieves high speed
double-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for gen-
eral applications.
The chip is designed to comply with the following key DDR2 SDRAM fea-
tures such as posted CAS with additive latency, write latency = read
latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Ter-
mination.
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. For example, 1Gb(x16)
device receive 13/10/3 addressing.
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power supply
and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 60ball FBGA(x8) and in 84ball
FBGA(x16).
NOTE : The functionality described and the timing specifications included in this data
sheet are for the DLL Enabled mode of operation.
NOTE : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device Operation & Timing
Diagram”.
-4-

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K4T1G164QG 전자부품, 판매, 대치품
K4T1G084QG
K4T1G164QG
3.3 FBGA Package Dimension (x8)
datasheet
Rev. 1.0
Industrial DDR2 SDRAM
Units : Millimeters
(Datum A)
A
(Datum B) B
C
D
E
F
G
H
J
K
L
60-0.48 Solder ball
(Post reflow 0.50 0.05)
0.2 M A B
7.50 ± 0.10
0.80 x 8 = 6. 40
3.20
0.80
1.60
987654321
A
# A1 INDEX MARK
B
(0.30)
MOLDING AREA
(0.60)
BOTTOM VIEW
7.50 ± 0.10
#A1
TOP VIEW
0.37±0.05
0.9±0.1
-7-

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