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기능 StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT
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G28F320J5-120 데이터시트, 핀배열, 회로
E
ADVANCE INFORMATION
INTEL StrataFlash™ MEMORY TECHNOLOGY
32 AND 64 MBIT
28F320J5 and 28F640J5
n High-Density Symmetrically-Blocked
Architecture
64 128-Kbyte Erase Blocks (64 M)
32 128-Kbyte Erase Blocks (32 M)
n 5 V VCC Operation
2.7 V I/O Capable
n Configurable x8 or x16 I/O
n 120 ns Read Access Time (32 M)
150 ns Read Access Time (64 M)
n Enhanced Data Protection Features
Absolute Protection with
VPEN = GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n Industry-Standard Packaging
µBGA* Package, SSOP and TSOP
Packages (32 M)
n Cross-Compatible Command Support
Intel Basic Command Set
Common Flash Interface
Scaleable Command Set
n 32-Byte Write Buffer
6 µs per Byte Effective
Programming Time
n 640,000 Total Erase Cycles (64 M)
320,000 Total Erase Cycles (32 M)
10,000 Erase Cycles per Block
n Automation Suspend Options
Block Erase Suspend to Read
Block Erase Suspend to Program
n System Performance Enhancements
STS Status Output
n Intel StrataFlash™ Memory Flash
Technology
Capitalizing on two-bit-per-cell technology, Intel StrataFlash™ memory products provide 2X the bits in 1X the
space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are
the first to bring reliable, two-bit-per-cell storage technology to the flash market.
Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash
memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result,
Intel StrataFlash components are ideal for code or data applications where high density and low cost are
required. Examples include networking, telecommunications, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design
migrations from existing 28F016SA/SV, 28F032SA, and Word-Wide FlashFile memory devices (28F160S5
and 28F320S5).
Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By
using the Common Flash Interface (CFI) and the Scaleable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel’s 0.4 micron ETOX™ V process technology, Intel StrataFlash memory provides the
highest levels of quality and reliability.
January 1998
Order Number: 290606-004




G28F320J5-120 pdf, 반도체, 판매, 대치품
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
E
FIGURES
Figure 1. Intel StrataFlash™ Memory Block
Diagram..............................................6
Figure 2. µBGA* Package (64-Mbit and 32-Mbit)9
Figure 3. TSOP Lead Configuration (32-Mbit) ..10
Figure 4. SSOP Lead Configuration (64-Mbit
and 32-Mbit) .....................................11
Figure 5. Memory Map .....................................12
Figure 6. Device Identifier Code Memory Map .14
Figure 7. Write to Buffer Flowchart...................34
Figure 8. Byte/Word Program Flowchart ..........35
Figure 9. Block Erase Flowchart ......................36
Figure 10. Block Erase Suspend/Resume
Flowchart.......................................... 37
Figure 11. Set Block Lock-Bit Flowchart...........38
Figure 12. Clear Block Lock-Bit Flowchart........39
Figure 13. Transient Input/Output Reference
Waveform for VCCQ = 5.0 V ± 10%
(Standard Testing Configuration)......45
Figure 14. Transient Input/Output Reference
Waveform for VCCQ = 2.7 V3.6V .....45
Figure 15. Transient Equivalent Testing Load
Circuit ...............................................45
Figure 16. AC Waveform for Read Operations .47
Figure 17. AC Waveform for Write Operations .49
Figure 18. AC Waveform for Reset Operation ..50
TABLES
Table 1. Lead Descriptions.................................7
Table 2. Chip Enable Truth Table.....................13
Table 3. Bus Operations...................................15
Table 4. Intel StrataFlash™ Memory Command
Set Definitions ...................................16
Table 5. Summary of Query Structure Output as
a Function of Device and Mode .........19
Table 6. Example of Query Structure Output of
a x16- and x8-Capable Device...........19
Table 7. Query Structure ..................................20
Table 8. Block Status Register .........................21
Table 9. CFI Identification ................................22
Table 10. System Interface Information ............23
Table 11. Device Geometry Definition ..............24
Table 12. Primary Vendor-Specific Extended
Query.................................................25
Table 13. Identifier Codes ................................26
Table 14. Write Protection Alternatives ............30
Table 15. Configuration Coding Definitions.......31
Table 16. Status Register Definitions ...............32
Table 17. eXtended Status Register Definitions33
Date of
Revision
09/01/97
09/17/97
12/01/97
1/31/98
Version
REVISION HISTORY
Description
-001
-002
-003
-004
Original Version
Modifications made to cover sheet
VCC/GND Pins Converted to No Connects specification change added
ICCS, ICCD, ICCW, and ICCE specification change added
Order Codes specification change added
The µBGA* chip-scale package in Figure 2 was changed to a 52-ball
package and appropriate documentation added. The 64-Mb µBGA
package dimensions were changed in Figure 2. Changed Figure 4 to
read SSOP instead of TSOP.
4 ADVANCE INFORMATION

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G28F320J5-120 전자부품, 판매, 대치품
E
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
Symbol
A0
A1–A22
DQ0–DQ7
DQ8–DQ15
CE0,
CE1,
CE2
RP#
OE#
WE#
STS
Table 1. Lead Descriptions
Type
Name and Function
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when the device
is in x8 mode. This address is latched during a x8 program cycle. Not used in
x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high).
INPUT
ADDRESS INPUTS: Inputs for addresses during read and program operations.
Addresses are internally latched during a program cycle.
32-Mbit: A0–A21
64-Mbit: A0–A22
INPUT/
OUTPUT
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and
inputs commands during Command User Interface (CUI) writes. Outputs array,
query, identifier, or status data in the appropriate read mode. Floated when the
chip is de-selected or the outputs are disabled. Outputs DQ6–DQ0 are also
floated when the Write State Machine (WSM) is busy. Check SR.7 (Status
Register bit 7) to determine WSM status.
INPUT/ HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming
OUTPUT operations. Outputs array, query, or identifier data in the appropriate read mode;
not used for Status Register reads. Floated when the chip is de-selected, the
outputs are disabled, or the WSM is busy.
INPUT CHIP ENABLES: Activates the device’s control logic, input buffers, decoders,
and sense amplifiers. When the device is de-selected (see Table 2, Chip Enable
Truth Table), power reduces to standby levels.
All timing specifications are the same for these three signals. Device selection
occurs with the first edge of CE0, CE1, or CE2 that enables the device. Device
deselection occurs with the first edge of CE0, CE1, or CE2 that disables the
device (see Table 2, Chip Enable Truth Table).
INPUT
RESET/ POWER-DOWN: Resets internal automation and puts the device in
power-down mode. RP#-high enables normal operation. Exit from reset sets the
device to read array mode. When driven low, RP# inhibits write operations which
provides data protection during power transitions.
RP# at VHH enables master lock-bit setting and block lock-bits configuration
when the master lock-bit is set. RP# = VHH overrides block lock-bits thereby
enabling block erase and programming operations to locked memory blocks. Do
not permanently connect RP# to VHH.
INPUT OUTPUT ENABLE: Activates the device’s outputs through the data buffers
during a read cycle. OE# is active low.
INPUT WRITE ENABLE: Controls writes to the Command User Interface, the Write
Buffer, and array blocks. WE# is active low. Addresses and data are latched on
the rising edge of the WE# pulse.
OPEN
DRAIN
OUTPUT
STATUS: Indicates the status of the internal state machine. When configured in
level mode (default mode), it acts as a RY/BY# pin. When configured in one of
its pulse modes, it can pulse to indicate program and/or erase completion. For
alternate configurations of the STATUS pin, see the Configurations command.
Tie STS to VCCQ with a pull-up resistor.
ADVANCE INFORMATION
7

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G28F320J5-120

StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT

Intel Corporation
Intel Corporation

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