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PDF QD17TL02 Data sheet ( Hoja de datos )
| Número de pieza | QD17TL02 | |
| Descripción | TFT LCD Module | |
| Fabricantes | Quanta | |
| Logotipo |  |
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Quanta Display Inc.
SPECIFICATION
3&6. 2CIG
Doc No. QD17TL0202
Doc. REV.: 03
Issue Date: 6/23/2005
RoHS Compliant
Specification for TFT LCD Module
Model No.
QD17TL02 Rev.:02
Approved By
Quanta Display Inc.
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4. Input Connectors
3&6. 2CIG
4-1 Signal Interface Connector
CN1 (2 channel, LVDS signals – NSC/Ti standard and +3.3V DC power supply)
Using connector: FI-XB30Sx-HFxx/FI-X30Sx-HFxx/equivalent (JAE)
Interface Cable Pin Assignments
PIN NO SYMBOL
FUNCTION
1 VSS
Ground
2 VDD
Power Supply, 3.3 V (typical)
3 VDD
Power Supply, 3.3 V (typical)
4
V EEDID
DDC 3.3V power
5 NC
Reserved for supplier test point
6
Clk EEDID
DDC Clock
7 DATA EEDID DDC Data
8 Rin0- - LVDS differential data input (R0-R5, G0) (odd pixels)
9 Rin0+ + LVDS differential data input (R0-R5, G0) (odd pixels)
10 VSS
Ground
11 Rin1-
- LVDS differential data input (G1-G5, B0-B1) (odd pixels)
12 Rin1+
+ LVDS differential data input (G1-G5, B0-B1) (odd pixels)
13 VSS
Ground
14 Rin2-
- LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
15 Rin2+
+ LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
16 VSS
Ground
17 ClkIN-
- LVDS differential clock input (odd pixels)
18 ClkIN+ + LVDS differential clock input (odd pixels)
19 VSS
Ground
20 Even_Rin0- - LVDS differential data input (R0-R5, G0) (even pixels)
21 Even_Rin0+ + LVDS differential data input (R0-R5, G0) (even pixels)
22 VSS
Ground
23 Even_Rin1- - LVDS differential data input (G1-G5, B0-B1) (even pixels)
24 Even_Rin1+ + LVDS differential data input (G1-G5, B0-B1) (even pixels)
25 VSS
Ground
26 Even_Rin2- - LVDS differential data input (B2-B5, HS, VS, DE) (even pixels)
27 Even_Rin2+ + LVDS differential data input (B2-B5, HS, VS, DE) (even pixels)
28 VSS
Ground
29 Even _Clk in- - LVDS differential clock input (even pixels), 2.1V
30 Even _Clk in+ + LVDS differential clock input (even pixels), 2.1V
[Note 1] Relation between LVDS signals and actual data shows below section (4-2).
[Note 2] The shielding case is connected with signal GND.
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7. Timing characteristics of LCD module input signals
7-1. Timing characteristics
(This is specified at digital outputs of LVDS driver.)
Data
ENAB
3&6. 2CIG
ዞ
Sync
ዟዠ
ዡ
ዝ
ዢ
ዄ Vertical ዅ
Itemዄsymbolዅ
Vsync cycle (TVA)
Blanking period(TVB)
Sync pulse width (TVC)
Back porch (TVD)
Sync pulse width + Back
porch (TVC+TVD)
Active display area (TVE)
Front porch (TVF)
Min.
16.71
910
10
3
5
8
900
2
Typ.
16.68
912
12
3
6
9
900
3
Max.
16.70
934
34
6
25
31
900
3
Unit Remark
ms Negative
line
line
line
line
line
line
line
( Horizontal )
Itemዄsymbolዅ
Min.
Typ.
Max. Unit Remark
Hsync cycle (THA)
18.36
1690
18.29
1760
17.87
1904
Ǵs Negative
clock
Blanking period (THB)
Sync pulse width (THC)
Back porch (THD)
Sync pulse width + Back
porch (THC +THD)
Active display area (THE)
Front porch (THF)
250
32
188
220
1440
30
320
32
224
256
1440
64
464 clock
152 clock
232 clock
384 clock
1440
80
clock
clock
ዄClock ዅ
Item
Min.
Typ.
Max. Unit Remark
Frequency
92.3 96.3 106.7 MHz [Note1/2]
[Note1] In case of lower frequency, the deterioration of display quality, flicker etc., may be
occurred.
[Note2] Two pixel-data are sampled at a same time.
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