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기능 MMC Controller and 64GB NAND Flash
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MYXFC64GJDDN 데이터시트, 핀배열, 회로
Micron Confidential and Proprietary
MMC C4oGnBt,r8oGllBe,rM1&6YGXNBFA,CN362D4GJBFDF:leaDeas·NMthu*MreCs
e·MMCMemory *Advanced information. Subject to change without notice.
MTFC4GLDDQ-4MMMIT,CMCToFnCt8rGoLllDeDr Qan-4dM6I4TGB NAND Flash
MTFFCe1at6uGreJsDDQ-4M IT, MTFC32GJDDQ-4M IT
Featu rTien-lsead ball metallurgy
• MultiMediaCard (MMC) controller and 64GB NAND Flash
• Multi MVeCdC:ia2C.7ar3d.6(VMMC) controller and NAND Flash
• 100-b aVllCLCQB(GduAa(l RvooltHagSe)6: /16.6-5–1.95V; 2.7–3.6V
comp liTaynptic)al current consumption
• VCC: 2.7ƒƒ3.S6tVandby current: 160μA
• VCCQ (duƒƒalAvcotivletacguerr)e:n1t (.R6M5–S1):.8905mVA; 2.7–3.6V
• Industrial temperature ranges
– OMpeMraCtin-g StepmepceriafitcureF:e–4a0t˚uCrteos+85˚C
– Storage temperature: –40˚C to +85˚C
• Typic alJcEuDrErCe/nMtMcConstsaunmdaprdtivoenrsion 4.41-compliant (JEDEC
– StanSdtbanydcaurdrrNeon. t8:47-0Aμ44A1()4-GSPBI,m8oGdBe)n; o9t0sµuApp(o1r6teGd B,
32GB(se)e www.jedec.org/sites/default/files/docs/JESD84-A441.pdf)
– Activeƒƒ cAudrvraenncted(R1M1-sSig)n: a7l0inmterAfa(c4eGB, 8GB); 90mA
(16GBƒƒ, 3x21,GxB4,)and x8 I/Os, selectable by host
ƒƒ MMC mode operation
MMC-SpƒƒeCcoimfmicanFdeclaastseus:rcelasss 0 (basic); class 2 (block read);
class 4 (block write); class 5 (erase); class 6 (write
• JEDEC/MMproCtescttaionn)d; calradssv7e(rlosciok nca4rd.)41-compliant
(JEDECƒSƒ taMnMdCaprldusNoa.n8d4M-AM4C4m1o)bileSPIprmotoocdoels not
supportƒeƒdT(esmepeowrarwy wwr.ijteedperocte.octriogn/sites/default/files/
docs/JEƒSƒD5824M-AH4z4c1lo.cpkdsfp)eed (MAX)
– AdvanƒƒceBdoo1t 1o-pseirgatnioanl(ihnigthe-rsfpaecede boot)
– x1, x4ƒ,ƒ aSnledepx8mIo/dOe s, selectable by host
– MMCƒƒmRoedpleayo-pproetreacttieodnmemory block (RPMB)
– Commƒƒ aSnedcucrelaesrassees:ancdlatsrism0 (basic); class 2 (block
read)ƒ;ƒclHaasrsdw4a(rbe lroescekt swigrniatle); class 5 (erase);
classƒ6ƒ (Mwurlititpeleppraorttiteiocntsiownith);ecnlhaasnsce7d(alottrcibkucteard)
– MMCƒpƒ lPuesrmaanenndt aMndMpoCwmero-obnilwerite pprrootetcoticoonls
– Tempƒoƒ rDaoruybwlerdiatetaprartoet(eDcDtRio) fnunction
– 52 MHƒƒ zHcigloh-cpkriosrpityeeindter(rMupAt (XHP) I)
– Boot ƒoƒpEenrhaatniocend(rheliiagbhle-swpriteeed boot)
– SleepƒƒmCoodnefigurable reliability settings
– Replaƒyƒ -pBarcoktgercotuend ompeermatioonry block (RPMB)
– Securƒeƒ eFruallysenahnandcetrdimconfigurable
– Hardƒwƒ aBreacrkewsaerdt -sciogmnpaaltible with previous MMC modes
– Mu ltEiCpCleapnadrbtiloticoknmsawnaigthemeennht aimnpcleemdeanttterdibute
– Permanent and power-on write protection
– Double data rate (DDR) function
– HMiYgXhFC-6p4rGiJoDrDiNty interrupt (HPI)
Revision 1.0 - 12/22/2014
FFigiguruer1e: e1·:MMMCicDreovnicee·MMC Device
MMC
power
MMC controller
MMC
interface
NAND Flash
power
NAND Flash
MMC-Specific Features (Continued)
––OptECiononhnsafingcuerdabrleeliraeblilaebwilritityesettings Marking
BPaacckkgargoeu(Snnd63opPbe3ra7tsioolnder)
FBmuaƒoclƒldky1(ew16es49anm-rhbmdaa-lxlncL1ocF8emBmdGpmAcaoxtni1b.f4liegmuwmr)iatbhleprevious MMBCG
• EC COapnerdatbinlgoTcekmmpearantaurgeement implemented
ƒƒ Industrial (-40°C TC +85°C)
IT
1
Form #: CSI-D-685 Document 004




MYXFC64GJDDN pdf, 반도체, 판매, 대치품
3 Signal Descriptions
MMC Controller & NAND Flash
MYXFC64JDDN*
*Advanced information. Subject to change without notice.
Table 2: Signal Descriptions
Symbol
CLK
RST_n
CMD
DAT[7:0]
VCC
VCCQ
VSS1
VSSQ1
VDDIM
NC
RFU
Type
Input
Input
I/O
I/O
Supply
Supply
Supply
Supply
Description
Clock: Each cycle of the clock directs a transfer on the command line and on the data line(s). The frequency can
vary between the minimum and the maximum clock frequency.
Reset: The RST_n signal is used by the host for resetting the device, moving the device to the preidle state.
By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD register byte 162,
bits[1:0] to 0x1 to enable this functionality before the host can use it.
Command: This signal is a bidirectional command channel used for command and response transfers. The CMD
signal has two bus modes: open-drain mode and push-pull mode (see Operating Modes). Commands are sent
from the MMC host to the device, and responses are sent from the device to the host.
Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull mode. By default, after
power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. The MMC controller can
configure a wider data bus for data transfer either using DAT[3:0] (4-bit mode) or DAT[7:0] (8-bit mode). e·MMC
includes internal pull-up resistors for data lines DAT[7:1]. Immediately after entering the 4-bit mode, the device
disconnects the internal pull-up resistors on the DAT[3:1] lines. Upon entering the 8-bit mode, the device
disconnects the internal pull-ups on the DAT[7:1] lines.
VCC: NAND interface (I/F) I/O and NAND Flash power supply.
VCCQ: e·MMC controller core and e·MMC I/F I/O power supply.
VSS: NAND I/F I/O and NAND Flash ground connection.
VSSQ: e·MMC controller core and e·MMC I/F ground connection.
Internal voltage node: At least a 0.1μF capacitor is required to connect VDDIM to ground. A 1μF capacitor
is recommended. Do not tie to supply voltage or ground.
No connect: No internal connection is present.
Reserved for future use: No internal connection is present. Leave it floating externally.
Note:
1. VSS and VSSQ are connected internally.
MYXFC64GJDDN
Revision 1.0 - 12/22/2014
4
Form #: CSI-D-685 Document 004

4페이지










MYXFC64GJDDN 전자부품, 판매, 대치품
MMC Controller & NAND Flash
Micron Confidential and Proprietary
MYXFC64JDDN*
6 ArchitectuArrechitecture
Figure 5: e·MMFigCurFeu4n:cet·iMonMaCl FBulnocctkioDnailaBglroacmk Diagram
e·MMC
4*GAdBva,nc8edGinBfor,m1at6ionG. SBub,je3ctA2toGrcchBhan:igteeew·McithtouMutrnCeotice.
RST_n
CMD
CLK
VDDIM
MMC
controller
Registers
OCR CSD RCA
CID ECSD DSR
VCC
VCCQ
DAT[7:0]
VSS1
VSSQ1
NAND Flash
Note: 1Note: 1. VSS and VSSQ are internally connected.
MMC Proto1c.o lVSISnadned pVSeSnQ dareenintteronafllyNcAonNneDcteFdl.ash Technology
6.1 MMC ProtTvoihcceeo.MlTIhMneCdpesroppteeocncifodicleaisntiitonnodefdpeNefiAnndNeesDnthtFeolfcatoshmhe mNTAeuNncihDcnaFtoiloalonshgpfyreoattoucroelsbinetcwluedeendainhothsteadnedviaced.e-
The device has an intelligent on-board controller that manages the MMC communica-
The MMC sptieocnifipcarotiotoncdoel.fines the communication protocol between a host and a device. The protocol is
independentTohf tehceoNnAtrNoDlleFrlaaslhsofehaatunredsleinscblulodcekdminathneagdeemviceen.tTfhuendcetivoicneshsauscahnaisntleolgligiceanlt bolno-cbkoaarldloccoan-troller
that managetsiothneaMnMd Cwecaormlemvuenliincagt.ioTnhepsroetmocaonl.agement functions require complex algorithms and
depend entirely on NAND Flash technology (generation or memory cell type).
TT(ghheeenseceroamntitoaronnllaeoTtgrrhehaemmelsheedoomneshtvotaifrcpunyenrdocclheectasileolnsnbtdsyslooplecrree.sk).qthmuTiehraeseneacdmgoeemvamincpeealengxhteamfaunlgndeoclnerttsiitohfntumhsnescsstueaiconmhdnasadnsienaplgtoeeegrnmincdeaanlelltbny,tlfoiumrcenklacyktaiooilnlnnogscNatihnAtioteNenmDrnaaiFnnllldyav,siwsmhiebatalekercintlhegonvoethlloinegmgy.
Defect andinEvrisribolertoMthaenhaosgt eprmoceesnstor.
6.2
Micron e·MMC incorporates advanced technology for defect and error management. If
Defect anaddEerferoctrivMe balnocakgiesmideennttified, the device completely replaces the defective block with
one of the spare blocks. This process is invisible to the host and does not affect data
e·MMC incorsppoarcaeteasllaodcvaatnecdefdortetchhenuosloegr.y for defect and error management. If a defective block is identified,
the device coTmhpeledteevlyicrepalalscoeisntchleudefseactbivueilbtl-oinckewrriothr ocnoerroefcthioenspcoardeeb(lEoCckCs). aTlhgiosrpitrhocmestsoiesninsvuisreibtlehatot the
host and doedsantaotinatffeegcrtitdyaitsa mspaaicnetaailnloecda.ted for the user.
To make the best use of these advanced technologies and ensure proper data loading
and storage over the life of the device, the host must exercise the following precautions:
MYXFC64GJDDN
Revision 1.0 - 12/22/2014
• Check the status after WRITE, READ, and ERASE operations.
• Avoid power-down during W7RITE and ERASE operations.
PDF: 09005aef8523caab
Form #: CSI-D-685 Document 004
Micron Technology, Inc. reserves the right to change products or specifications without notice.

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MYXFC64GJDDN

MMC Controller and 64GB NAND Flash

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