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Número de pieza | C8051F300 | |
Descripción | Mixed Signal ISP Flash MCU Family | |
Fabricantes | Silicon Laboratories | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de C8051F300 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! C8051F300/1/2/3/4/5
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 8-Bit ADC ('F300/2 only)
• Up to 500 ksps
• Up to 8 external inputs
• Programmable amplifier gains of 4, 2, 1, & 0.5
• VREF from external pin or VDD
• Built-in temperature sensor
• External conversion start input
- Comparator
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current (<0.5 µA)
On-chip Debug
- On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug (no emulator
required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Complete development kit
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 6.6 mA @ 25 MHz;
14 µA @ 32 kHz
- Typical stop mode current: 0.1 µA
- Temperature range: –40 to +85 °C
High Speed 8051 µc Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 256 bytes internal data RAM
- Up to 8 kB (‘F300/1/2/3), 4 kB (‘F304), or 2 kB
(‘F305) Flash; 512 bytes are reserved in the 8 kB
devices
Digital Peripherals
- 8 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART and SMBus™ serial
ports
- Three general-purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with three
capture/compare modules
- Real time clock mode using PCA or timer and
external clock source
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
supports UART operation
- External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
- Can switch between clock sources on-the-fly; Useful
in power saving modes
11-Pin QFN or 14-Pin SOIC Package
- QFN Size = 3x3 mm
ANALOG
PERIPHERALS
A 8-bit
M PGA 500 ksps
U
X
ADC
C8051F300/2 only
TEMP
+ SENSOR
- VOLTAGE COMPARATOR
DIGITAL I/O
UART
SMBus
PCA
Timer 0
Timer 1
Timer 2
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
8/4/2 kBytes
ISP Flash
12
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR WDT
Rev. 2.9 7/08
Copyright © 2008 by Silicon Laboratories
C8051F300/1/2/3/4/5
1 page C8051F300/1/2/3/4/5
13.4.Using the SMBus............................................................................................ 115
13.4.1.SMBus Configuration Register............................................................... 116
13.4.2.SMB0CN Control Register ..................................................................... 119
13.4.3.Data Register ......................................................................................... 122
13.5.SMBus Transfer Modes.................................................................................. 123
13.5.1.Master Transmitter Mode ....................................................................... 123
13.5.2.Master Receiver Mode ........................................................................... 124
13.5.3.Slave Receiver Mode ............................................................................. 125
13.5.4.Slave Transmitter Mode ......................................................................... 126
13.6.SMBus Status Decoding................................................................................. 127
14. UART0.................................................................................................................... 131
14.1.Enhanced Baud Rate Generation................................................................... 132
14.2.Operational Modes ......................................................................................... 133
14.2.1.8-Bit UART ............................................................................................. 133
14.2.2.9-Bit UART ............................................................................................. 134
14.3.Multiprocessor Communications .................................................................... 135
15. Timers.................................................................................................................... 143
15.1.Timer 0 and Timer 1 ....................................................................................... 143
15.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 143
15.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 145
15.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 145
15.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 146
15.2.Timer 2 .......................................................................................................... 151
15.2.1.16-bit Timer with Auto-Reload................................................................ 151
15.2.2.8-bit Timers with Auto-Reload................................................................ 152
16. Programmable Counter Array ............................................................................. 155
16.1.PCA Counter/Timer ........................................................................................ 156
16.2.Capture/Compare Modules ............................................................................ 157
16.2.1.Edge-triggered Capture Mode................................................................ 158
16.2.2.Software Timer (Compare) Mode........................................................... 159
16.2.3.High Speed Output Mode....................................................................... 160
16.2.4.Frequency Output Mode ........................................................................ 161
16.2.5.8-Bit Pulse Width Modulator Mode......................................................... 162
16.2.6.16-Bit Pulse Width Modulator Mode....................................................... 163
16.3.Watchdog Timer Mode ................................................................................... 164
16.3.1.Watchdog Timer Operation .................................................................... 164
16.3.2.Watchdog Timer Usage ......................................................................... 165
16.4.Register Descriptions for PCA........................................................................ 167
17. C2 Interface ........................................................................................................... 173
17.1.C2 Interface Registers.................................................................................... 173
17.2.C2 Pin Sharing ............................................................................................... 175
Document Change List............................................................................................. 176
Contact Information.................................................................................................. 178
Rev. 2.9
5
5 Page C8051F300/1/2/3/4/5
List of Registers
SFR Definition 5.1. AMX0SL: AMUX0 Channel Select (C8051F300/2) . . . . . . . . . . . . 42
SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2) . . . . . . . . . . . . . . . 43
SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2) . . . . . . . . . . . . . . . . . . . 43
SFR Definition 5.4. ADC0CN: ADC0 Control (C8051F300/2) . . . . . . . . . . . . . . . . . . . . 44
SFR Definition 5.5. ADC0GT: ADC0 Greater-Than Data Byte (C8051F300/2) . . . . . . 46
SFR Definition 5.6. ADC0LT: ADC0 Less-Than Data Byte (C8051F300/2) . . . . . . . . . 46
SFR Definition 6.1. REF0CN: Reference Control Register . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 54
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 54
SFR Definition 8.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SFR Definition 8.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 8.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SFR Definition 8.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 8.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR Definition 8.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SFR Definition 8.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SFR Definition 8.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 77
SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 78
SFR Definition 8.11. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 79
SFR Definition 8.12. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SFR Definition 9.1. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SFR Definition 10.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 10.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 10.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 11.1. OSCICL: Internal Oscillator Calibration . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 11.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 11.3. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 100
SFR Definition 12.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 12.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 12.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 108
SFR Definition 12.4. P0: Port0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 12.5. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 12.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 110
SFR Definition 13.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 118
SFR Definition 13.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SFR Definition 13.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SFR Definition 14.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SFR Definition 14.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 137
SFR Definition 15.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SFR Definition 15.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SFR Definition 15.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Rev. 2.9
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet C8051F300.PDF ] |
Número de pieza | Descripción | Fabricantes |
C8051F300 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
C8051F301 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
C8051F302 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
C8051F303 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
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