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PDF HS-2420EH Data sheet ( Hoja de datos )
| Número de pieza | HS-2420EH | |
| Descripción | Radiation Hardened Fast Sample and Hold | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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DATASHEET
Radiation Hardened Fast Sample and Hold
HS-2420EH
The HS-2420EH is a radiation hardened monolithic circuit
consisting of a high performance operational amplifier with its
output in series with an ultra-low leakage analog switch and a
MOSFET input unity gain amplifier.
With an external hold capacitor connected to the switch
output, a versatile high performance sample-and-hold or
track-and-hold circuit is formed. When the switch is closed, the
device behaves as an operational amplifier and any of the
standard op amp feedback networks may be connected
around the device to control gain, frequency response, etc.
When the switch is opened, the output will remain at its last
level.
Performance as a sample-and-hold compares very favorably
with other monolithic, hybrid, modular and discrete circuits.
Accuracy to better than 0.01% is achievable over the
temperature range. Fast acquisition is coupled with superior
droop characteristics, even at high temperatures. High slew
rate, wide bandwidth and low acquisition time produce
excellent dynamic characteristics. The ability to operate at
gains greater than 1 frequently eliminates the need for
external scaling amplifiers.
The device may also be used as a versatile operational
amplifier with a gated output for applications such as analog
switches, peak holding circuits, etc.
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95669.
Features
• Electrically screened to SMD #5962-95669
• QML qualified per MIL-PRF-38535 requirements
• Maximum acquisition time
- 10V Step to 0.1% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4µs
- 10V Step to 0.01% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6µs
• Maximum drift current . . . . . . . . . . . . . . . . . . . . . . . . . . . 10nA
(maximum over-temperature)
• TTL compatible control input
• Power supply rejection . . . . . . . . . . . . . . . . . . . . . . . . . 80dB
• Radiation tolerance
- High dose rate (50 to 300rad(Si)/s) . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . 100krad(Si)*
* Only the EH device is wafer-by-wafer acceptance tested at
the low dose rate and guaranteed to 50krad(Si). The
100krad(Si) limit is established by characterization only.
• No latch-up
Applications
• Data acquisition systems
• D to A deglitcher
• Auto zero systems
• Peak detector
• Gated op amp
OFFSET
ADJUST
34
V+
5
- INPUT 1
+ INPUT
2
-
+
-
+
7
OUTPUT
14
SAMPLE/
HOLD
CONTROL
HS-2420EH
13 5
11
GND V- HOLD
CAPACITOR
FIGURE 1. FUNCTIONAL DIAGRAM
March 17, 2015
FN8727.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
Timing Waveforms
VIN
(POS tACQ CASE)
0V
S/H CONTROL 0V
HS-2420EH
10V
2V
0.01% OR 0.1%
ENVELOPE
DUT OUTPUT
(POS tACQ CASE)
0V
(t1 DIGITIZER COMMAND)
t1
(t2 DIGITIZER COMMAND)
t2
t1 10µs
t2
+V
0V
+OS, tR
+V
-V
+SL
FIGURE 7. TIMING DIAGRAM FOR ACQUISITION TIME, (POSITIVE tACQ CASE)
INPUT
0V
-OS, tF
-V
VPEAK
90%
10%
VFINAL
90%
tR tF
FIGURE 8A.
FIGURE 8. OVERSHOOT, RISE AND FALL TIME WAVEFORMS
FIGURE 8B.
INPUT
FIGURE 9A.
+V
-V
-SL
+V
75%
25%
-V
FIGURE 9. SLEW RATE WAVEFORMS
t t
FIGURE 9B.
10V
10%
VFINAL
VPEAK
+V
25%
75%
-V
Submit Document Feedback
5
FN8727.0
March 17, 2015
5 Page 
HS-2420EH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
-A- -D-
E
-B-
bbb S C A - B S D S
c1 LEAD FINISH
BASE
METAL
(c)
b1
MM
(b)
SECTION A-A
BASE
PLANE
SEATING
PLANE
D
S1
b2
b
AA
e
ccc M C A - B S D S
S2 Q
-C- A
L
eA
eA/2
c
aaa M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be mea-
sured at the centroid of the finished lead surfaces, when solder dip
or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a par-
tial lead paddle. For this configuration dimension b3 replaces di-
mension b2.
5. Dimension Q shall be measured from the seating plane to the base
plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
- 0.200 - 5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
- 0.785 - 19.94
-
E
0.220
0.310
5.59
7.87
-
e 0.100 BSC
2.54 BSC
-
eA 0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1 0.005 - 0.13 - 6
S2 0.005 - 0.13 - 7
90o 105o 90o 105o
-
aaa
- 0.015 - 0.38
-
bbb
- 0.030 - 0.76
-
ccc
- 0.010 - 0.25
-
M
-
0.0015
-
0.038
2
N 14
14 8
Rev. 0 4/94
Submit Document Feedback 11
FN8727.0
March 17, 2015
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HS-2420EH.PDF ] | |
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