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PDF 56F805 Data sheet ( Hoja de datos )
| Número de pieza | 56F805 | |
| Descripción | 16-bit Digital Signal Controllers | |
| Fabricantes | Freescale Semiconductor | |
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Hay una vista previa y un enlace de descarga de 56F805 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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56F805
Data Sheet
Preliminary Technical Data
56F800
16-bit Digital Signal Controllers
DSP56F805
Rev. 16
09/2007
freescale.com
1 page  
56F805 Description
• Two General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins
• CAN 2.0 B Module with 2-pin port for transmit and receive
• Two Serial Communication Interfaces, each with two pins (or four additional GPIO lines)
• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)
• 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins
• Computer Operating Properly (COP) watchdog timer
• Two dedicated external interrupt pins
• External reset input pin for hardware reset
• External reset output pin for system reset
• JTAG/On-Chip Emulation (OnCE™) module for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
1.2 56F805 Description
The 56F805 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact
program code, the 56F805 is well-suited for many applications. The 56F805 includes many peripherals
that are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
MCU and DSP applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F805 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F805 also provides two external
dedicated interrupt lines, and up to 32 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F805 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It
also supports program execution from external memory (64K).
Freescale Semiconductor
56F805 Technical Data, Rev. 16
5
5 Page 
2.3 Clock and Phase Locked Loop Signals
Clock and Phase Locked Loop Signals
Table 2-5 PLL and Clock
No. of
Pins
1
1
Signal
Name
EXTAL
Signal
Type
Input
XTAL Input/O
utput
State During
Reset
Input
Chip-driven
Signal Description
External Crystal Oscillator Input—This input should be
connected to an 8MHz external crystal or ceramic resonator. For
more information, please refer to Section 3.5.
Crystal Oscillator Output—This output should be connected to
an 8MHz external crystal or ceramic resonator. For more
information, please refer to Section 3.5.
This pin can also be connected to an external clock source. For
more information, please refer to Section 3.5.3.
1 CLKO Output Chip-driven Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
Table 2-6 Address Bus Signals
No. of
Pins
6
2
Signal
Name
A0–A5
A6–A7
GPIOE2–
GPIOE3
Signal
Type
Output
Output
Input/O
utput
State During
Reset
Tri-stated
Tri-stated
Input
Signal Description
Address Bus—A0–A5 specify the address for external
Program or Data memory accesses.
Address Bus—A6–A7 specify the address for external
Program or Data memory accesses.
Port E GPIO—These two General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15 Output
Tri-stated
Address Bus—A8–A15 specify the address for external
Program or Data memory accesses.
Input
GPIOA0– Input/O
Port A GPIO—These eight General Purpose I/O (GPIO) pins
GPIOA7 utput
can be individually be programmed as input or output pins.
After reset, the default state is Address Bus.
Freescale Semiconductor
56F805 Technical Data, Rev. 16
11
11 Page | ||
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