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IS24C01-3 데이터시트 PDF




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부품번호 IS24C01-3 기능
기능 1024-BIT SERIAL ELECTRICALLY ERASABLE PROM
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IS24C01-3 데이터시트, 핀배열, 회로
IS24C01-3
IS24C01-3
1,024-BIT SERIAL ELECTRICALLY
ERASABLE PROM
ISSIISSI®®
ADVANCE INFORMATION
APRIL 1998
FEATURES
• Low power CMOS
— Active current less than 2 mA
— Standby current less than 8 µA
• Low voltage operation
— 3.0V (Vcc = 2.7V to 5.5V)
• Hardware write protection
— Write control pin
• Internally organized as 128 x 8
• Two-wire serial interface
— Bidirectional data transfer protocol
• 8-Byte page-write mode
— Minimized total write time per byte
• 100 KHz at 3V; 400 KHz at 5V
• Automatic word address incrementing
— Sequential register read
• Self-timed write cycle
— Maximum write cycle time of 10 ms
• Endurance: 100K cycles per byte
• 8-pin PDIP or SOIC packages
• Filtered inputs for noise suppression
OVERVIEW
The IS24C01-3 is a low cost 1,024-bit serial EEPROM. It
is fabricated using ISSI’s advanced CMOS EEPROM
technology and operates from a single supply.
The IS24C01-3 is internally organized as a 128 x 8
memory bank. The IS24C01-3 features a serial interface
and software protocol allowing operation on a simple
2-wire bus. Up to eight IS24C01-3s may be connected to
the 2-wire bus by programming the A0, A1, and A2 inputs.
FUNCTIONAL BLOCK DIAGRAM
Vcc 8
SDA 5
SCL 6
WC 7
A2 3
A1 2
A0 1
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
Load Inc.
WORD ADDRESS
COUNTER
HIGH VOLTAGE
GENERATOR,
TIMING AND
CONTROL
32 x 32
32 MEMORY
CORE
32
Y
DECODER
GND 4
nMOS
ACK
Clock
DATA
DI/O REGISTER
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE013-0A
04/17/98
1




IS24C01-3 pdf, 반도체, 판매, 대치품
IS24C01-3
Random Access Read
Random Address READ operation allows the master
device to access any memory location in a random fashion.
This operation involves a two-step process. First, the
master device generates a START condition and initiates
Device Addressing Byte with a WRITE operation (read/
write bit sets to “0”), followed by the address of the data
word the master device is to READ. This procedure stores
the desired address of data word to the internal address
counter of the IS24C01-3.
After the data word address ACKnowledge is received by
the master device, the master device now initiates a
CURRENT ADDRESS READ by sending Device
Addressing Byte with a READ operation (read/write bit
sets to “1”). The IS24C01-3 responds with an ACKnowledge
and transmits the eight data bits stored at the address
location where the master device is to READ. At this point,
the master device terminates the operation by pulling
ACKnowledge HIGH (lack of ACKnowledge) indicating the
last data word to be read, followed by a STOP condition.
(Refer to Figure 8. Random Address Read Diagram.)
ISSI®
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. The first data
word is transmitted as with the other byte read modes, the
master device now responds with an ACKnowledge indicating
that it requires additional data from the IS24C01-3. The
IS24C01-3 continues to output data for each ACKnowledge
received. the master device terminates the sequential
READ operation by pulling ACKnowledge HIGH (lack of
ACKnowledge) indicating the last data word to be read,
followed by a STOP condition.
The data output is sequential, with the data from
address n followed by the date from address n+1, ... etc.
The address counter increments by one automatically,
allowing the entire memory contents to be serially read
during sequential read operation. When the memory
address boundry (address 127) is reached, the address
counter “rolls over” to address 0, and the IS24C01-3
continues to output data for each ACKnowledge received.
(Refer to Figure 9. Sequential Read Operation Starting
with a Random Address READ Diagram.)
SDA
SCL
Master
Transmitter/
Receiver
Vcc
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Figure 1. Typical System Bus Configuration
Master
Transmitter/
Receiver
SCL from
Master
Data Output
from
Transmitter
Data Output
from
Receiver
4
1 89
tAA
Figure 2. ACKnowledge Response from Receiver
ACK
tAA
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EP013-0A
04/17/98

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IS24C01-3 전자부품, 판매, 대치품
IS24C01-3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
VS Supply Voltage
0 to +7.0
V
VP Voltage on Any Pin
–0.5 to Vcc + 0.5 V
TBIAS
Temperature Under Bias
–40 to +85
°C
TSTG
TSOL
Storage Temperature
–65 to +150
Soldering Temperature (less than 10 sec)
300
°C
°C
IOUT Output Current
5 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
2.7V to 5.5V
2.7V to 5.5V
CAPACITANCE(1,2)
Symbol Parameter
Conditions
Max.
Unit
CIN Input Capacitance
VIN = 0V
5 pF
COUT
Output Capacitance
VOUT = 0V
8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
ISSI®
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION EE013-0A
04/17/98
7

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