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XE162FM 데이터시트 PDF




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부품번호 XE162FM 기능
기능 16-Bit Single-Chip Real Time Signal Controller
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XE162FM 데이터시트, 핀배열, 회로
16-Bit
Architecture
XE162FM, XE162HM
16-Bit Single-Chip
Real Time Signal Controller
XE166 Family Derivatives / Base Line
Data Sheet
V2.0 2009-03
Microcontrollers




XE162FM pdf, 반도체, 판매, 대치품
XE162FM, XE162HM
XE166 Family Derivatives / Base Line
XE162xM
Revision History: V2.0, 2009-03
Previous Version(s):
V1.3, 2008-11
V1.2, 2008-09
V1.1, 2008-06 Preliminary
V1.0, 2008-06 (Intermediate version)
Page
Subjects (major changes since last revision)
15ff Overlaid analog input channels specified (ADC0/ADC1)
69, 71
Current through power domain DMP_A specified
76 Specification of wakeup clock frequencies improved
88f Section “Pad Properties” added
90f SSC interface timing improved
93ff Debug interface timing detailled
Trademarks
C166, TriCore, and DAVEare trademarks of Infineon Technologies AG.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
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Data Sheet
V2.0, 2009-03

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XE162FM 전자부품, 판매, 대치품
XE162FM, XE162HM
XE166 Family Derivatives / Base Line
Summary of Features
16-Bit Single-Chip
Real Time Signal Controller
XE162xM (XE166 Family)
1 Summary of Features
For a quick overview and easy reference, the features of the XE162xM are summarized
here.
• High-performance CPU with five-stage pipeline and MPU
– 12.5 ns instruction cycle at 80 MHz CPU clock (single-cycle execution)
– One-cycle 32-bit addition and subtraction with 40-bit result
– One-cycle multiplication (16 × 16 bit)
– Background division (32 / 16 bit) in 21 cycles
– One-cycle multiply-and-accumulate (MAC) instructions
– Enhanced Boolean bit manipulation facilities
– Zero-cycle jump execution
– Additional instructions to support HLL and operating systems
– Register-based design with multiple variable register banks
– Fast context switching support with two additional local register banks
– 16 Mbytes total linear address space for code and data
– 1024 Bytes on-chip special function register area (C166 Family compatible)
– Integrated Memory Protection Unit (MPU)
• Interrupt system with 16 priority levels for up to 96 sources
– Selectable external inputs for interrupt generation and wake-up
– Fastest sample-rate 12.5 ns
• Eight-channel interrupt-driven single-cycle data transfer with
Peripheral Event Controller (PEC), 24-bit pointers cover total address space
• Clock generation from internal or external clock sources,
using on-chip PLL or prescaler
• Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip
Memory Areas
• On-chip memory modules
– 8 Kbytes on-chip stand-by RAM (SBRAM)
– 2 Kbytes on-chip dual-port RAM (DPRAM)
– Up to 16 Kbytes on-chip data SRAM (DSRAM)
– Up to 32 Kbytes on-chip program/data SRAM (PSRAM)
– Up to 576 Kbytes on-chip program memory (Flash memory)
– Memory content protection through Error Correction Code (ECC)
• On-Chip Peripheral Modules
– Multi-functional general purpose timer unit with 5 timers
Data Sheet
7 V2.0, 2009-03

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