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GAL16V8D-25LJI 데이터시트 PDF




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부품번호 GAL16V8D-25LJI 기능
기능 High Performance E2CMOS PLD Generic Array Logic
제조업체 Lattice Semiconductor
로고 Lattice Semiconductor 로고


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GAL16V8D-25LJI 데이터시트, 핀배열, 회로
GAL16V8
High Performance E2CMOS PLD
Generic Array Logic™
Features
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
3.5 ns Maximum Propagation Delay
Fmax = 250 MHz
3.0 ns Maximum from Clock Input to Data Output
UltraMOS® Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
75mA Typ Icc on Low Power Device
45mA Typ Icc on Quarter Power Device
ACTIVE PULL-UPS ON ALL PINS
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
EIGHT OUTPUT LOGIC MACROCELLS
Maximum Flexibility for Complex Logic Designs
Programmable Output Polarity
Also Emulates 20-pin PAL® Devices with Full
Function/Fuse Map/Parametric Compatibility
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
100% Functional Testability
APPLICATIONS INCLUDE:
DMA Control
State Machine Control
High Speed Graphics Processing
Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL16V8, at 3.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL16V8 are the PAL architectures listed
in the table of the macrocell description section. GAL16V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
I/CLK
CLK
I
I
I
I
I
I
I
I
Pin Configuration
I
I4
PLCC
I I/CLK Vcc I/O/Q
2 20
18
I/O/Q
I GAL16V8 I/O/Q
I6
16 I/O/Q
Top View
I I/O/Q
I8
9
14 I/O/Q
11 13
I GND I/OE I/O/Q I/O/Q
I/CLK
I
I
I
I
I
I
I
I
GND
SOIC
1 20
GAL
5 16V8
Top 15
View
10 11
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
OE
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
DIP
I/CLK
I
I
I
I
I
I
I
I
GND
1 20 Vcc
I/O/Q
GAL
16V8
5
I/O/Q
I/O/Q
I/O/Q
15 I/O/Q
I/O/Q
I/O/Q
I/O/Q
10 11 I/OE
Copyright © 2001 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
May 2001
16v8_08
1




GAL16V8D-25LJI pdf, 반도체, 판매, 대치품
Specifications GAL16V8
Registered Mode
In the Registered mode, macrocells are configured as dedicated Dedicated input or output functions can be implemented as sub-
registered outputs or as I/O functions.
sets of the I/O function.
Architecture configurations available in this mode are similar to the
common 16R8 and 16RP4 devices with various permutations of
polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/O's are possible in this mode.
Registered outputs have eight product terms per output. I/O's have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.
CLK
DQ
XOR Q
OE
XOR
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
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GAL16V8D-25LJI 전자부품, 판매, 대치품
Specifications GAL16V8
Complex Mode Logic Diagram
DIP & PLCC Package Pinouts
1
2128
0 4 8 12 16 20 24 28 PTD
0000
0224
2
OLMC
XOR-2048
AC1-2120
0256
0480
3
OLMC
XOR-2049
AC1-2121
0512
0736
4
OLMC
XOR-2050
AC1-2122
0768
0992
5
1024
1248
6
OLMC
XOR-2051
AC1-2123
OLMC
XOR-2052
AC1-2124
1280
1504
7
OLMC
XOR-2053
AC1-2125
1536
1760
8
OLMC
XOR-2054
AC1-2126
1792
2016
9
OLMC
XOR-2055
AC1-2127
2191
SYN-2192
AC0-2193
19
18
17
16
15
14
13
12
11
7

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부품번호상세설명 및 기능제조사
GAL16V8D-25LJ

High Performance E2CMOS PLD Generic Array Logic

Lattice Semiconductor
Lattice Semiconductor
GAL16V8D-25LJI

High Performance E2CMOS PLD Generic Array Logic

Lattice Semiconductor
Lattice Semiconductor

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