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GAL18V10-20LP PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 GAL18V10-20LP
기능 High Performance E2CMOS PLD Generic Array Logic
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GAL18V10-20LP 데이터시트, 핀배열, 회로
GAL18V10
High Performance E2CMOS PLD
Generic Array Logic™
Features
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
7.5 ns Maximum Propagation Delay
Fmax = 111 MHz
5.5 ns Maximum from Clock Input to Data Output
TTL Compatible 16 mA Outputs
UltraMOS® Advanced CMOS Technology
LOW POWER CMOS
75 mA Typical Icc
ACTIVE PULL-UPS ON ALL PINS
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
TEN OUTPUT LOGIC MACROCELLS
Uses Standard 22V10 Macrocell Architecture
Maximum Flexibility for Complex Logic Designs
PRELOAD AND POWER-ON RESET OF REGISTERS
100% Functional Testability
APPLICATIONS INCLUDE:
DMA Control
State Machine Control
High Speed Graphics Processing
Standard Logic Speed Upgrade
ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
The GAL18V10, at 7.5 ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide a very flexible 20-pin
PLD. CMOS circuitry allows the GAL18V10 to consume much less
power when compared to its bipolar counterparts. The E2 technol-
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
By building on the popular 22V10 architecture, the GAL18V10
eliminates the learning curve usually associated with using a new
device architecture. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell (OLMC)
to be configured by the user. The GAL18V10 OLMC is fully com-
patible with the OLMC in standard bipolar and CMOS 22V10 de-
vices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Functional Block Diagram
I/CLK
I
I
I
I
I
I
I
RESET
8
OLMC
8
OLMC
8
OLMC
8
OLMC
10
OLMC
10
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
PRESET
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Pin Configuration
PLCC
I
I4
I I/CLK Vcc I/O/Q
2 20
18 I/O/Q
I I/O/Q
I 6 GAL18V10 16 I/O/Q
I
Top View
I/O/Q
I8
14 I/O/Q
9 11 13
I/O/Q GND I/O/Q I/O/Q I/O/Q
DIP
I/CLK
I
I
I
I
I
I
I
I/O/Q
GND
1 20 Vcc
I/O/Q
GAL
18V10
5
I/O/Q
I/O/Q
I/O/Q
15 I/O/Q
I/O/Q
I/O/Q
I/O/Q
10 11 I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
18v10_03
1




GAL18V10-20LP pdf, 반도체, 판매, 대치품
Registered Mode
S0 = 0
S1 = 0
AR
DQ
CLK
Q
SP
ACTIVE LOW
Combinatorial Mode
Specifications GAL18V10
AR
DQ
CLK
Q
SP
S0 = 1
S1 = 0
ACTIVE HIGH
S0 = 0
S1 = 1
ACTIVE LOW
S0 = 1
S1 = 1
ACTIVE HIGH
4

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GAL18V10-20LP 전자부품, 판매, 대치품
Specifications GAL18V10B
AC Switching Characteristics
Over Recommended Operating Conditions
PARAM.
TEST
COND.1
DESCRIPTION
tpd A Input or I/O to Comb. Output
tco A Clock to Output Delay
tcf2 Clock to Feedback Delay
tsu Setup Time, Input or Fdbk before Clk
th Hold Time, Input or Fdbk after Clk
A Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
COM
COM
COM
COM
-7 -10 -15 -20
UNITS
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
7.5 10 15 20 ns
5.5 7 10 12 ns
3.5 3.5 7 10 ns
5.5 6 8 12 ns
0 0 0 0 ns
90.9 76.9 55.5 41.6 MHz
fmax3 A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
111 105 66.7 45.4 MHz
A Maximum Clock Frequency with
No Feedback
111 105 66.7 62.5 MHz
twh Clock Pulse Duration, High
twl Clock Pulse Duration, Low
ten B Input or I/O to Output Enabled
tdis C Input or I/O to Output Disabled
tar A Input or I/O to Asynch. Reset of Reg.
tarw Asynch. Reset Pulse Duration
tarr Asynch. Reset to ClkRecovery Time
tspr Synch. Preset to ClkRecovery Time
4
4
8
8
13
8
8
10
46 8
46 8
10 15 20
9 15 20
13 20 20
8 10 15
8 10 15
10 10 12
ns
ns
ns
ns
ns
ns
ns
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
C Input Capacitance
I
CI/O I/O Capacitance
*Characterized but not 100% tested.
MAXIMUM*
8
8
UNITS
pF
pF
TEST CONDITIONS
V = 5.0V, V = 2.0V
CC I
VCC = 5.0V, VI/O = 2.0V
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