PDF GAL20LV8 Data sheet ( Hoja de datos )

Número de pieza	GAL20LV8
Descripción	Low Voltage E2CMOS PLD Generic Array Logic
Fabricantes	Lattice Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de GAL20LV8 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas
No Preview Available ! I2nT0poNLulVeet8wsrDao5nnVt GAL20LV8 Low Voltage E2CMOS PLD Generic Array Logic™ Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 2.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology — TTL-Compatible Balanced 8mA Output Drive • 3.3V LOW VOLTAGE 20V8 ARCHITECTURE — JEDEC-Compatible 3.3V Interface Standard — 5V Compatible Inputs • ACTIVE PULL-UPS ON ALL PINS • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention • EIGHT OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs — Programmable Output Polarity • PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability • APPLICATIONS INCLUDE: — Glue Logic for 3.3V Systems — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade • ELECTRONIC SIGNATURE FOR IDENTIFICATION Description The GAL20LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL20LV8D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which com- bines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be repro- grammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configura- tions possible with the GAL20LV8D are the PAL architectures listed in the table of the macrocell description section. GAL20LV8D devices are capable of emulating any of these PAL architectures with full function/fuse map compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and function- ality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. I/CLK I I I I I I I I I I IMUX CLK 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC 8 OLMC OE IMUX Pin Configuration PLCC 4 I5 I I7 NC I9 I I 11 12 2 28 GAL20LV8D Top View 14 16 26 25 I/O/Q I/O/Q 23 I/O/Q NC 21 I/O/Q I/O/Q 19 I/O/Q 18 I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I I/OE Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com March 2000 20lv8_05 1 1 page Specifications GAL20LV8 Registered Mode Logic Diagram PLCC Package Pinout 2 2640 0 4 8 12 16 20 24 28 32 36 P T D 3 0000 0280 4 0320 0600 5 0640 0920 6 0960 1240 7 1280 1560 9 1600 1880 10 1920 2200 11 2240 2520 12 13 2703 64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... .... 2630, 2631 Byte7 Byte6 .... .... Byte1 Byte0 MSB LSB OLMC XOR-2560 AC1-2632 OLMC XOR-2561 AC1-2633 27 26 25 OLMC XOR-2562 AC1-2634 OLMC XOR-2563 AC1-2635 OLMC XOR-2564 AC1-2636 24 23 21 OLMC XOR-2565 AC1-2637 OLMC XOR-2566 AC1-2638 OLMC XOR-2567 AC1-2639 20 19 18 17 OE 16 SYN-2704 AC0-2705 5 5 Page Specifications GAL20LV8 AC Switching Characteristics Over Recommended Operating Conditions TEST PARAMETER COND1. DESCRIPTION tpd2 A Input or I/O to Combinational Output tco2 A Clock to Output Delay tcf3 — Clock to Feedback Delay tsu — Setup Time, Input or Feedback before Clock↑ th — Hold Time, Input or Feedback after Clock↑ A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) COM COM COM -3 -5 -7 UNITS MIN. MAX. MIN. MAX. MIN. MAX. 1 3.5 1 5 1 7.5 ns 1 2.5 1 3 1 5 ns — 2 — 2 — 3 ns 3 — 4 — 5 — ns 0 — 0 — 0 — ns 180 — 142.8 — 100 — MHz fmax4 A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 200 — 166 — 125 — MHz A Maximum Clock Frequency with No Feedback 250 — 166 — 125 — MHz twh4 twl4 ten — Clock Pulse Duration, High — Clock Pulse Duration, Low B Input or I/O to Output Enabled B OE to Output Enabled 2 — 3 — 4 — ns 2 — 3 — 4 — ns — 4.5 — 6 — 3.5 — 5 — 7.5 ns — 6.5 ns tdis C Input or I/O to Output Disabled C OE to Output Disabled — 4.5 — 6 — 3.5 — 5 — 7.5 ns — 6.5 ns 1) Refer to Switching Test Conditions section. 2) Minimum values for tpd and tco are not 100% tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance TYPICAL 5 5 UNITS pF pF TEST CONDITIONS VCC = 3.3V, VI = 0V VCC = 3.3V, VI/O = 0V 11 11 Page

Páginas	Total 17 Páginas
PDF Descargar	[ Datasheet GAL20LV8.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
GAL20LV8	Low Voltage E2CMOS PLD Generic Array Logic	Lattice Semiconductor
GAL20LV8D-3LJ	Low Voltage E2CMOS PLD Generic Array Logic	Lattice Semiconductor
GAL20LV8D-5LJ	Low Voltage E2CMOS PLD Generic Array Logic	Lattice Semiconductor
GAL20LV8D-7LJ	Low Voltage E2CMOS PLD Generic Array Logic	Lattice Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar