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AT24C512C 데이터시트 PDF




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부품번호 AT24C512C 기능
기능 EEPROM
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AT24C512C 데이터시트, 핀배열, 회로
AT24C512C
I2C-Compatible (2-wire) Serial EEPROM
512-Kbit (65,536 x 8)
DATASHEET
Features
Low-voltage and Standard-voltage Operation
̶ VCC = 1.7V to 3.6V
̶ VCC = 2.5V to 5.5V
Internally Organized as 65,536 x 8 (512K)
I2C-Compatible (2-Wire) Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400kHz (1.7V) and 1MHz (2.5V, 5.5V) Compatibility
Write Protect Pin for Hardware Data Protection
128-byte Page Write Mode
̶ Partial Page Writes Allowed
Random and Sequential Read Modes
Self-timed Write Cycle (5ms Max)
High Reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 40 Years
Green Package Options (Pb/Halide-free/RoHS Compliant)
̶ 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-pad UDFN,
8-ball WLCSP, and 8-ball VFBGA Packages
Die sale Options: Wafer Form and Tape and Reel Available
Description
The Atmel® AT24C512C provides 524,288 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 65,536 words of
8 bits each. The cascadable feature of the device allows up to eight devices to
share a common 2-wire bus. The device is optimized for use in many industrial
and commercial applications where low-power and low-voltage operation are
essential. The devices are available in space-saving 8-lead JEDEC SOIC, 8-lead
EIAJ SOIC, 8-lead TSSOP, 8-pad UDFN, 8-ball WLCSP, and 8-ball VFBGA
packages. In addition, the entire family is available in 1.7V to 3.6V and 2.5V to
5.5V versions.
Atmel-8720F-SEEPROM-AT24C512C-Datasheet_012015




AT24C512C pdf, 반도체, 판매, 대치품
5. Memory Organization
AT24C512C, 512-Kbit Serial EEPROM: The 512K is internally organized as 512 pages of 128 bytes each.
Random word addressing requires a 16-bit data word address.
5.1 Pin Capacitance
Table 5-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 5.5V.
Symbol Test Condition
Max
CI/O
CIN
Note:
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
1. This parameter is characterized and is not 100% tested.
8
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
5.2 DC Characteristics
Table 5-2. DC Characteristics
Applicable over recommended operating range from: TAI = -40C to +85C, VCC = 1.7V to 3.6V or 2.5V to 5.5V (unless
otherwise noted).
Symbol
VCC1
VCC2
ICC1
ICC2
ISB1
ISB2
ILI
ILO
VIL
VIH
VOL1
VOL2
Parameter
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Standby Current
Standby Current
Input Leakage Current
Output Leakage
Current
Input Low Level(1)
Input High Level(1)
Output Low Level
Output Low Level
Test Condition
VCC = 3.6V
Read at 400kHz
Write at 400kHz
VCC = 5.0V
Read at 400kHz
Write at 400kHz
VCC = 1.7V
VCC = 3.6V
VIN = VCC or VSS
VCC = 2.5V
VCC = 5.5V
VIN = VCC or VSS
VIN = VCC or VSS
Min
1.7
2.5
VOUT = VCC or VSS
VCC = 1.7V
VCC = 3.0V
IOL = 0.15mA
IOL = 2.1mA
-0.6
VCC x 0.7
Typ
0.10
0.05
Max Units
3.6 V
5.5 V
1.0 mA
3.0 mA
2.0 mA
3.0 mA
1.0 μA
3.0 μA
2.0 μA
6.0 μA
3.0 μA
3.0 μA
VCC x 0.3
VCC + 0.5
0.2
0.4
V
V
V
V
Note: 1. VIL min and VIH max are reference only, and are not tested.
4 AT24C512C [DATASHEET]
Atmel-8720F-SEEPROM-AT24C512C-Datasheet_012015

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AT24C512C 전자부품, 판매, 대치품
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
Figure 6-3. Output Acknowledge
SCL
1
89
Data In
Data Out
Start
Acknowledge
Standby Mode: The AT24C512C features a low-power standby mode, which is enabled:
Upon power-up and
After the receipt of the Stop condition and the completion of any internal operations.
Software Reset: After an interruption in protocol, power loss, or system reset, any 2-wire part can be protocol
reset by following these steps:
1. Create a Start condition (if possible).
2. Clock nine cycles.
3. Create another Start condition followed by a Stop condition, as shown in Figure 6-4 below.
The device should be ready for the next communication after above steps have been completed. In the event
that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to reset
the device.
Figure 6-4. Software Reset
Dummy Clock Cycles
SCL 1 2 3
Start
Condition
SDA
89
Start
Condition
Stop
Condition
AT24C512C [DATASHEET]
Atmel-8720F-SEEPROM-AT24C512C-Datasheet_012015
7

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