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MT8870D 데이터시트 PDF




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부품번호 MT8870D 기능
기능 Integrated DTMF Receiver
제조업체 Zarlink Semiconductor
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MT8870D 데이터시트, 핀배열, 회로
MT8870D/MT8870D-1
ISO2-CMOS Integrated DTMF Receiver
Data Sheet
Features
October 2006
• Complete DTMF Receiver
• Low power consumption
• Internal gain setting amplifier
• Adjustable guard time
• Central office quality
• Power-down mode
• Inhibit mode
• Backward compatible with MT8870C/MT8870C-1
Applications
• Receiver system for British Telecom (BT) or
CEPT Spec (MT8870D-1)
• Paging systems
• Repeater systems/mobile radio
• Credit card systems
• Remote control
• Personal computers
• Telephone answering machine
Ordering Information
MT8870DE
18 Pin PDIP
MT8870DS
18 Pin SOIC
MT8870DN
20 Pin SSOP
MT8870DSR
18 Pin SOIC
MT8870DNR
20 Pin SSOP
MT8870DN1
20 Pin SSOP*
MT8870DE1
18 Pin PDIP*
MT8870DS1
18 Pin SOIC*
MT8870DNR1 20 Pin SSOP*
MT8870DSR1 18 Pin SOIC*
MT8870DE1-1 18 Pin PDIP*
MT8870DS1-1 18 Pin SOIC*
MT8870DSR1-1 18 Pin SOIC*
*Pb Free Matte Tin
-40°C to +85°C
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Tubes
Tubes
Tape & Reel
Description
The MT8870D/MT8870D-1 is a complete DTMF
receiver integrating both the bandsplit filter and digital
decoder functions. The filter section uses switched
capacitor techniques for high and low group filters;
the decoder uses digital counting techniques to detect
and decode all 16 DTMF tone-pairs into a 4-bit code.
VDD VSS
VRef
INH
PWDN
IN +
IN -
GS
Bias
Circuit
Chip Chip
Power Bias
Dial
Tone
Filter
VRef
Buffer
High Group
Filter
Zero Crossing
Detectors
Low Group
Filter
Digital
Detection
Algorithm
Code
Converter
and Latch
to all
Chip
Clocks
St Steering
GT Logic
OSC1
OSC2
St/GT
ESt
Figure 1 - Functional Block Diagram
STD
TOE
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Q1
Q2
Q3
Q4




MT8870D pdf, 반도체, 판매, 대치품
MT8870D/MT8870D-1
Data Sheet
Decoder Section
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the
incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm
protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency
deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the
detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry
specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition
will cause ESt to assume an inactive state (see “Steering Circuit”).
VDD
VDD
St/GT
ESt
StD
MT8870D/
MT8870D-1
C
vc
R
ttGGTTAP==((RRCC))IInn([VVDDDD//(VVTDSDt)-VTSt)]
Figure 4 - Basic Steering Circuit
Steering Circuit
Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt
causes vc (see Figure 4) to rise as the capacitor discharges. Provided signal condition is maintained (ESt remains
high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and
drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the
output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been
registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state
control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between
signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal
interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting
the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system
requirements.
Guard Time Adjustment
In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown
in Figure 4 is applicable. Component values are chosen according to the formula:
tREC=tDP+tGTP
tID=tDA+tGTA
4
Zarlink Semiconductor Inc.

4페이지










MT8870D 전자부품, 판매, 대치품
MT8870D/MT8870D-1
C1 R1
MT8870D/
IN+ MT8870D-1
+
-
IN-
C2 R4
R3
R5 GS
R2 VRef
DC1if=feCr2e=n1t0ianl FInput Amplifier
RR12==6R04k=R,5=R130=037k.5 k
All resistors are ±1% tolerance.
All capacitors are ±5% tolerance.
R3=
R2R5
R2+R5
VOLTAGE GAIN (Av diff)=
R5
R1
INPUT IMPEDANCE
(ZINDIFF) = 2
R12+
1
ωc
2
Figure 6 - Differential Input Configuration
OSC1
X-tal
To OSC1 of next
C MT8870D/MT8870D-1
OSC2
OSC2
C
OSC1
C=30 pF
X-tal=3.579545 MHz
Figure 7 - Oscillator Connection
Data Sheet
7
Zarlink Semiconductor Inc.

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