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PDF AKD4357 Data sheet ( Hoja de datos )
| Número de pieza | AKD4357 | |
| Descripción | 192kHz 24-Bit 6ch DAC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK4357]
AK4357
192kHz 24-Bit 6ch DAC with DSD Input
GENERAL DESCRIPTION
The AK4357 is six channels 24bit DAC corresponding to digital audio system. Using AKM's advanced
multi bit architecture for its modulator the AK4357 delivers a wide dynamic range while preserving
linearity for improved THD+N performance. The AK4357 has full differential SCF outputs, removing the
need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The
AK4357 accepts 192kHz PCM data and 1-Bit DSD data, ideal for a wide range of applications including
DVD-Audio and SACD.
F EATURES
o Sampling Rate Ranging from 8kHz to 192kHz
o 24Bit 8 times Digital Filter with Slow roll-off option
o THD+N: -90dB
o DR, S/N: 106dB
o High Tolerance to Clock Jitter
o Low Distortion Differential Output
o DSD Data input available
o Channel Independent Digital De-emphasis for 32, 44.1 & 48kHz sampling
o Zero Detect function
o Channel Independent Digital Attenuator with soft-transition (3 Speed
mode)
o Soft Mute
o 3-wire Serial Interface for Volume Control
o Master clock: 256fs, 384fs, 512fs or 768fs (PCM Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (PCM Double Speed Mode)
128fs or 192fs (PCM Quad Speed Mode)
512fs or 768fs (DSD Mode)
o Power Supply: 4.75 to 5.25V
o 48pin LQFP Package
DZF
LOUT1+
LOUT1-
ROUT1+
ROUT1-
LOUT2+
LOUT2-
ROUT2+
ROUT2-
LOUT3+
LOUT3-
ROUT3+
ROUT3-
Audio
SCF DAC DATT
I/F
SCF DAC DATT
SCF DAC DATT
SCF DAC DATT
PCM
Control
Register
SCF DAC DATT
SCF DAC DATT
AK4357
DSD
MCLK
LRCK
BICK
SDTI1
SDTI2
SDTI3
CSN
CCLK
CDTI
DCLK
DSDL1
DSDR1
DSDL2
DSDR2
DSDL3
DSDR3
MS0088-E-02
- 1-
2002/07
1 page  
ASAHI KASEI
[AK4357]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=5V; VREF=AVDD; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; RL≥4kΩ ; unless otherwise specified)
Parameter
min typ max Units
Resolution
24 Bits
Dynamic Characteristics
(Note 4)
THD+N
fs=44.1kHz
0dBFS
-90 -86 dB
BW=20kHz
fs=96kHz
0dBFS
-88 -84 dB
BW=40kHz
- dB
fs=192kHz
0dBFS
-86 - dB
BW=40kHz
- dB
Dynamic Range (-60dBFS with A-weighted) (Note 5)
100
106
dB
S/N (A-weighted)
(Note 6)
100 106
dB
Interchannel Isolation (1kHz)
90 100
dB
Interchannel Gain Mismatch
0.2 0.5 dB
DC Accuracy
Gain Drift
Output Voltage
Load Resistance
(Note 7)
(Note 8)
100 - ppm/°C
±2.35
±2.5
±2.65
Vpp
4 kΩ
Power Supplies
Power Supply Current (AVDD+DVDD)
Normal Operation (PDN = “H”, fs ≤96kHz)
50 75 mA
Normal Operation (PDN = “H”, fs=192kHz)
60 85 mA
Power-Down Mode (PDN = “L”)
(Note 9)
10 100 µA
Note: 4. Measured by Audio Precision System Two. Refer tothe evaluation board manual.
5. 100dB at 16bit data.
6. S/N is independent of input bit length.
7. Fu ll scale voltage (0dB). Output voltage scales with the voltage of VREFH pin.
AOUT(typ.@0dB)=(AOUT+) -(AOUT-)=±2.5Vpp*VREFH/5.0
8. For AC-load. 8kΩ for DC-load
9. All digital inputs including clock pins (MCLK, BICK and LRCK) are held DVDD or DVSS.
MS0088-E-02
- 5-
2002/07
5 Page 
ASAHI KASEI
[AK4357]
LRCK
fs
88.2kHz
96.0kHz
128fs
11.2896MHz
12.2880MHz
MCLK
192fs
256fs
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
384fs
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
fs
176.4kHz
192.0kHz
MCLK
128fs
192fs
22.5792MHz 33.8688MHz
24.5760MHz 36.8640MHz
BICK
64fs
11.2896MHz
12.2880MHz
Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK
512fs
768fs
256fs
384fs
128fs
192fs
Sampling Speed
Normal
Double
Quad
Table 6. Sampling Speed (Auto Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
-
-
-
-
-
22.5792
24.5760
192fs
-
-
-
-
-
33.8688
36.8640
MCLK (MHz)
256fs
384fs
--
--
--
22.5792 33.8688
24.5760 36.8640
--
--
512fs
16.3840
22.5792
24.5760
-
-
-
-
768fs
24.5760
33.8688
36.8640
-
-
-
-
Sampling Speed
Normal
Double
Quad
Table 7. System Clock Example (Auto Setting Mode)
2) DSD Mode
The external clocks, which are required to operate the AK4357, are MCLK and DCLK. The master clock (MCLK) should be
synchronized with DSD clock (DCLK) but the phase is not critic al. The frequency of MCLK is set by DCKS bit.
All external clocks (MCLK, DCLK) should always be present whenever the AK4357 is in the normal operation mode
(PDN= ”H”). If these clocks are not provided, the AK4357 may draw excess current because the device utilizes dynamic
refreshed logic internally. The AK4357 should be reset by PDN= ”L” after threse clocks are provided. If the external clocks
are not present, the AK4357 should be in the power-down mode (PDN= ”L”). After exiting reset(PDN = “↑”) at power-up
etc., the AK4357 is in the power-down mode until MCLK is input. PCM interface signals (BICK, LRCK, SDTI1-3) are fixed to
“H” or “L”.
DCKS
MCLK
DCLK
0
512fs
64fs
1
768fs
64fs
Table 8. System Clock (fs=44.1kHz)
MS0088-E-02
- 11 -
2002/07
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet AKD4357.PDF ] | |
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