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PAS6371LT 데이터시트 PDF




Pixart Imaging에서 제조한 전자 부품 PAS6371LT은 전자 산업 및 응용 분야에서
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부품번호 PAS6371LT 기능
기능 CMOS VGA DIGITAL IMAGE SENSOR
제조업체 Pixart Imaging
로고 Pixart Imaging 로고


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PAS6371LT 데이터시트, 핀배열, 회로
PAS6371LT Specification
PAS6371LT CMOS VGA DIGITAL IMAGE SENSOR
General Description
The PAS6371LT is a highly integrated CMOS active-pixel image sensor that has a VGA YUV output of 640
x 480 pixels. It embedded the new FinePixel™ sensor technology to perform the excellent image quality.
PAS6371LT outputs YUV/YCbCr 4:2:2 or RGB565/555/444 data through a parallel data bus. It is available in
29-pin CSP.
Features
ƒ Resolution: 640 x 480 pixels
ƒ Bayer-RGB color filter array
ƒ Output format (8-bit):
z YUV/YCbCr 4:2:2 (VGA,
QVGA … )
z RGB565/555/444 (VGA, QVGA … )
ƒ On-chip 10-bit pipelined A/D converter
ƒ On-chip 2-stage background compensation
DAC
ƒ Continuous variable frame time & exposure
time
ƒ I2CTM Interface
ƒ Flash light timing
ƒ Support 1.8V~3.3V I/O power
ƒ 10uA low power-down dissipation
(VDD-A = VDD-IO = 2.8V, VDD-C = 1.8V)
ƒ Automatic Background Compensation
ƒ AEC & AGC function
ƒ DSP function:
z AWB
z Gamma
z Color matrix
z Sharpness
z De-noise
z Color saturation
z Defect compensation
z Lens shading compensation
ƒ WOI & Sub-sampling
ƒ Critical Register table backward compatible
with PAS6311
Key Specification
Resolution
Analog
Power
I/O
Core
Pixel Size
Lens Chief Ray Angle
Frame rate
Max. System clock
Max. Pixel clock
Sensitivity
Color filter
Exposure Time
Scan Mode
S/N Ratio
Dynamic range
Package
640 (H) x 480 (V)
2.5V ~ 3.0V
1.8V ~ 3.3V
1.8V
4.5µmx4.5µm
28degree
30fps, VGA YUV mode
48MHz
24MHz, VGA YUV mode
2.1V/(Lux*Sec)
RGB Bayer Pattern
~ Frame time to Line time
Progressive
41dB
60dB
29-pin CSP
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
V1.1,
1
2008/04/09




PAS6371LT pdf, 반도체, 판매, 대치품
PixArt Imaging Inc.
PAS6371LT
2. Specifications
Absolute Maximum Ratings
Ambient Storage Temperature
Supply Voltage ( with respect to ground )
VDDD
VDDMA
VDDMD
All Input / Output Voltage ( with respect to ground )
Lead-free temperature, Surface-mount process
ESD rating, Human Body model
CMOS Image Sensor IC
-25 ~125
3.0V
4.5V
4.5V
-0.3V to VDDMD+0.5V
245
2000V
DC Electrical Characteristics ( Ta = 0 ~ 70 )
Symbol
Parameter
Min. Typ. Max.
Type : POWER
VDDMA
VDDD
VDDMD
IDD
IPWDN
DC supply voltage – Analog
2.5 2.8
DC supply voltage – Digital core
1.62 1.8
DC supply voltage – I/O
1.62
Operating Current (see Notea)
29
Power Down Current (see Noteb)
10
Type : IN & I/O Reset and System Clock(input clock)
3.0
1.98
3.3
20
VIH
Input Voltage HIGH
VDDMD
* 0.7
VIL Input Voltage LOW
VDDMD
* 0.3
Type : OUT & I/O for PX0 : 9, SDA, H/VSYNC and PXCLK(output clock)
VOH
Output Voltage HIGH
VDDMD
* 0.9
VOL Output Voltage LOW
Notea: VDDMA=2.8V, VDDD=1.8V, VDDMD=3.3V, 30fps VGA YUV output, without I/O loading
Noteb: VDDMA=2.8V, VDDMD=3.3V
VDDMD
* 0.1
Unit
V
V
V
mA
µA
V
V
V
V
AC Operating Condition
Symbol
fsysclk
tsysclk_dc
Parameter
System clock frequency
System clock duty cycle
Min. Typ. Max. Unit
24 MHz
45 55 %
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
V1.1,
4
2008/04/09

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PAS6371LT 전자부품, 판매, 대치품
PixArt Imaging Inc.
PAS6371LT
CMOS Image Sensor IC
4. I2CTM Bus
PAS6371LT supports I2C bus transfer protocol and acts as slave device. The 7-bits unique slave address
is “1000000” and supports receiving / transmitting speed as maximum 400KHz.
I2C Bus Overview
z Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the
devices connected to the I2C bus. Normally both SDA and SCL lines are open collector
structure and pulled high by external pull-up resistors.
z Only the master can initiates a transfer ( start ), generates clock signals, and terminates a
transfer ( stop ).
z Start and stop condition : A high to low transition of the SDA line while SCL is high defines a
start condition. A low to high transition of the SDA line while SCL is high defines a stop
condition. Please refer to Figure 2.1.
z Valid data : The data on the SDA line must be stable during the high period of the SCL clock.
Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the
first byte. Please refer to Figure 2.2.
z Both the master and slave can transmit and receive data from the bus.
z Acknowledge : The receiving device should pull down the SDA line during high period of the
SCL clock line when a complete byte was transferred by transmitter. In the case of a master
received data from a slave, the master does not generate an acknowledgment on the last byte
to indicate the end of a master read cycle.
Figure 2.1 Start and Stop conditions
Figure 2.2 Valid Data
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
V1.1,
7
2008/04/09

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부품번호상세설명 및 기능제조사
PAS6371LT

CMOS VGA DIGITAL IMAGE SENSOR

Pixart Imaging
Pixart Imaging

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