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PDF QT1103 Data sheet ( Hoja de datos )
| Número de pieza | QT1103 | |
| Descripción | 10-KEY SENSOR IC | |
| Fabricantes | QUANTUM | |
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lQ
QT1103
QTOUCH™ 10-KEY SENSOR IC
This datasheet is applicable to all revision 3 chips
The QT1103 is designed for low cost appliance, mobile, and consumer
electronics applications.
QTouch™ technology is a type of patented charge-transfer sensing
method well known for its robust, stable, EMC-resistant characteristics.
It is the only all-digital capacitive sensing technology in the market
today. This technology has over a decade of applications experience
spanning thousands of designs.
QTouch circuits are renowned for simplicity, reliability, ease of design,
and cost effectiveness.
QTouch™ sensors employ a single reference capacitor tied to two pins
of the chip for each sensing key; a signal trace leads from one of the
pins to the sensing electrode which forms the key. The sensing
electrode can be a simple solid shape such as a rectangle or circle. An
LED can be placed near or inside the solid circle for illumination.
The key electrodes can be designed into a conventional Printed Circuit
Board (PCB) or Flexible Printed Circuit Board (FPCB) as a copper
pattern, or as printed conductive ink on plastic film.
24 23 22 21 20 19 18 17
SNS8
SNS8K
SNS9
SNS9K
N/C
/CHANGE
1W
RX
25
26
27
28
29
30
31
32
QT1103
1 234 56 78
16 SNS5
15 SNS4K
14 SNS4
13 SNS3K
12 SNS3
11 SNS2K
10 SNS2
9 SNS1K
AT A GLANCE
Number of keys:
1 to 10
Technology:
Patented spread-spectrum charge-transfer (one-per-key mode)
Key outline sizes:
5mm x 5mm or larger (panel thickness dependent); widely different sizes and shapes possible
Key spacings:
6mm or wider, center to center (panel thickness, human factors dependent)
Electrode design:
Single solid or ring shaped electrodes; wide variety of possible layouts
Layers required:
One layer substrate; electrodes and components can be on same side
Substrates:
Electrode materials:
FR-4, low cost CEM-1 or FR-2 PCB materials; polyamide FPCB; PET films, glass
Copper, silver, carbon, ITO, Orgacon† ink (virtually anything electrically conductive)
Panel materials:
Plastic, glass, composites, painted surfaces (low particle density metallic paints possible)
Adjacent Metal:
Compatible with grounded metal immediately next to keys
Panel thickness:
Up to 50mm glass, 20mm plastic (key size dependent)
Key sensitivity:
Settable via change in reference capacitor (Cs) value
Outputs:
RS-232 based serial output, capable of single-wire operation
Moisture tolerance:
Good
Power:
2.8V ~ 5.0V
Package:
32-pin 5 x 5mm QFN RoHS compliant
Signal processing:
Self-calibration, auto drift compensation, noise filtering, AKS™
Applications:
Portable devices, domestic appliances and A/V gear, PC peripherals, office equipment
Patents:
AKS™ (patented Adjacent Key Suppression)
QTouch™ (patented Charge-transfer method)
†Orgacon is a registered trademark of Agfa-Gevaert N.V
AVAILABLE OPTIONS
TA
-400C to +850C
32-QFN
QT1103-ISG
LQ
CCopyright © 2006-2007 QRG Ltd
QT1103_3R0.03_0607
1 page  
1.3 Wiring
Pin Name
1 SS
2 /RST
3 Vdd
4 OSC
5 n/c
6 SNS0
7 SNS0K
8 SNS1
9 SNS1K
10 SNS2
11 SNS2K
12 SNS3
13 SNS3K
14 SNS4
15 SNS4K
16 SNS5
17 SNS5K
18 SNS6
19 SNS6K
20 SNS7
21 SNS7K
22 Vss
23 SYNC/LP‡
24 DETECT
25 SNS8
26 SNS8K
27 SNS9
28 SNS9K
29 n/c
30 /CHANGE
31 1W
32 RX
Type
OD
I
P
I
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
I
O/OD
I/O
I/O
I/O
I/O
-
OD
I/OD
I
Table 1.1 Pin Descriptions
Function
Spread spectrum
Reset input
Power
Oscillator
-
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin
Sense pin
Sense pin
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin and
mode select
Sense pin and mode
or option select
Sense pin
Ground
Sync In or LP In
Detect Status
Sense pin
Sense pin
Sense pin
Sense pin
-
State changed
1W mode serial I/O
2W Receive
Notes
Spread spectrum drive
Active low reset
+2.8 ~ +5.0V
Resistor to Vdd and optional
spread spectrum RC network
Leave open
To Cs0 and/or
option resistor
To Cs0 + Key
To Cs1 and/or
option resistor*
To Cs1 + Key
To Cs2 and/or
option resistor*
To Cs2 + Key
To Cs3 and/or
option resistor*
To Cs3 + Key
To Cs4
To Cs4 + Key
To Cs5 and/or
option resistor *
To Cs5 + Key
To Cs6 and/or
option resistor*
To Cs6 + Key and/or
mode resistor†
To Cs7 and/or mode resistor†
or option resistor*
To Cs7 + Key
0V
Rising edge sync or LP pulse
See Table 1.4
To Cs8
To Cs8 + Key
To Cs9
To Cs9 + Key
-
0 = a key state has changed
Requires pull-up
Requires pull-up to Vdd
Input for 2W mode
If Unused
100k
resistor to Vss
-
-
-
-
Open or
option resistor*
Open
Open or
option resistor*
Open
Open or
option resistor*
Open
Open or
option resistor*
Open
Open
Open
Open or
option resistor*
Open
Open or
option resistor*
Open or
mode resistor†
Open or mode resistor† or option
resistor*
Open
-
Vdd or Vss**
Open
Open
Open
Open
Open
Open
100k
resistor to Vss
-
Vdd
Pin Type
I
I/O
OD
I/OD
O/OD
P
CMOS input only
CMOS I/O
CMOS open drain output
CMOS input or open drain output
CMOS push-pull or open-drain output (option selected)
Ground or power
Notes
† Mode resistor is required only in Simplified mode (see Figure 1.2)
* Option resistor is required only in Full Options mode (see Figure 1.1)
‡ Pin is either Sync or LP depending on options selected (functions SL_0, SL_1, see Figure 1.1)
** See text
Lq
5
QT1103_3R0.03_0607
5 Page 
After sending the ‘P’ character
the host must immediately
float the 1W signal to prevent
a drive conflict between the
host and the QT1103 (see
Figure 2.6). The delay from
the received stop bit to the
QT1103 driving the 1W pin is
in the range 1-3 bit periods,
so the host should float the
pin within one bit period to
prevent a drive conflict.
Figure 2.8 UART Response Pattern on 1W Pin
1W floating
(from QT1103)
Serial bits
S01234567S
floating
floating
S01234567S
Associated key #
012345* *
6 7 8 9UU * *
(shown with keys 0, 2 and 7 detecting)
* Fixed bit values
U - Unused bits
Data Reply: Before sending a
reply, the QT1103 returns the /CHANGE signal to its inactive
(float-high) state.
The QT1103 then replies by sending two eight-bit characters
to the host over the 1W line using the same baud rate as the
request. With no keys pressed, both reply bytes are ASCII
‘@’ (0x40) characters; any keys that are pressed at the time
of the reply result in their associated bits being set in the
reply. Figure 2.8 shows the reply bytes when keys 0, 2 and 7
are pressed - 0x45, 0x42, and the associations between keys
and bits in the reply.
The QT1103 floats the 1W pin again after establishing the
level of the stop bit.
2.11.3 LP Mode Effects on 1W
The use of low power (LP) mode presents some additional
1W timing requirements. In LP mode (Section 2.5), the
QT1103 will only respond to a request from the host when it
is making one of its infrequent checks for a key press. Hence,
in that condition most requests from the host to the QT1103
will be ignored, since the QT1103 will be sleeping and
unresponsive. However, if either /CHANGE or DETECT are
active the QT1103 will be at full speed, and hence will always
respond to ‘P’ requests.
Note that when sleeping in LP mode, there are by definition
no keys active, so there should not be a reason for the host
to send the ‘P’ query command in the first place.
• Neither /CHANGE nor DETECT used. The host polls
the device regularly to obtain key status, with a
timeout in operation when awaiting the reply to each
‘P’ request. Not receiving a reply within the timeout
period only occurs when the part is sleeping, and
hence when no keys are active. Before triggering LP
mode the host should wait for all keys to become
inactive and then send an additional 'P' request to the
QT1103 to ensure /CHANGE is also inactive.
2.11.4 2W Operation
1W operation, as described in Section 2.11.3, requires that
the host float the 1W line while awaiting a reply from the
QT1103; this is not always possible.
To solve this problem, the QT1103 can also receive the ‘P’
character from the host on its ‘Rx’ pin separately from the 1W
pin (Figure 2.9). The host need not float the Rx line since the
QT1103 will never try to drive it.
Following a ‘P’ on Rx, the QT1103 will send the same
response pattern (Figure 2.8) over the 1W line as in pure 1W
mode.
All other comments and timings given for 1W operation are
applicable for 2W operation. LP operation is the same for 2W
mode as for 1W.
If the Rx pin is not used, it must be tied to Vdd.
Three strategies are available to the host to ensure that LP
mode operates correctly:
3 Design Notes
• /CHANGE used. The host monitors /CHANGE, and
only sends a ‘P’ request when it is low. The part is
awake by definition when /CHANGE is low. If
/CHANGE is high, key states are known to be
unchanged since the last reply received from the
QT1103, and so additional ‘P’ requests are not
needed. Before triggering LP mode the host should
3.1 Oscillator Frequency
The QT1103’s internal oscillator runs from an external
network connected to the OSC and SS pins as shown in
Figures 1.1 and 1.2. The charts in these figures show the
recommended values to use depending on nominal operating
voltage and spread spectrum mode.
wait for /CHANGE to go high after all keys have
become inactive.
• DETECT used. The host
If spread spectrum mode is not used, only resistor Rb1
should be used, the Css capacitor eliminated, and the SS pin
pulled to Vss with a 100k resistor.
monitors DETECT, and if it is
active (i.e. the part is awake) it
Figure 2.9 2W Operation
polls the device regularly to
obtain key status. When
DETECT is inactive (the part
may be sleeping) no requests
key state
change
request
from host
(1 byte)
driven reply
(from QT1103)
(2 bytes)
are sent because it is known
that no keys are active. Before
RX
(from host)
triggering LP mode the host
should wait for DETECT to
become inactive, and then
1W
(from QT1103)
floating
floating
send one additional 'P' request
to ensure /CHANGE is also
/CHANGE floating
floating
made inactive.
1 ~ 3 bit periods
Lq
11
QT1103_3R0.03_0607
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet QT1103.PDF ] | |
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