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PDF STD3PK50Z Data sheet ( Hoja de datos )
| Número de pieza | STD3PK50Z | |
| Descripción | P-CHANNEL MOSFET | |
| Fabricantes | STMicroelectronics | |
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STD3PK50Z
P-channel 500 V, 3 Ω typ., 2.8 A Zener-protected SuperMESH™
Power MOSFET in a DPAK package
Datasheet — production data
Features
Order code VDSS RDS(on)max ID
PTOT
STD3PK50Z 500 V < 4Ω 2.8 A 70 W
■ Gate charge minimized
■ Extremely high dv/dt capability
■ 100% avalanche tested
■ Very low intrinsic capacitance
■ Improved ESD capability
Applications
■ Switching applications
Description
This device is a P-channel Zener-protected Power
MOSFET developed using STMicroelectronics’
SuperMESH™ technology, achieved through
optimization of ST’s well established strip-based
PowerMESH™ layout. In addition to a significant
reduction in on-resistance, this device is designed
to ensure a high level of dv/dt capability for the
most demanding applications.
TAB
3
1
DPAK
Figure 1. Internal schematic diagram
or TAB
Table 1. Device summary
Order code
STD3PK50Z
Marking
3PK50Z
Package
DPAK
AM11279v1
Packaging
Tape and reel
Note:
For the P-channel Power MOSFETs actual polarity of voltages and current has to be
reversed.
August 2012
This is information on a product in full production.
Doc ID 18280 Rev 2
1/15
www.st.com
15
1 page  
STD3PK50Z
Electrical characteristics
Table 6. Switching times
Symbol
Parameter
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Min. Typ. Max. Unit
16 ns
VDD = 250 V, ID = 1.4 A,
RG=4.7 Ω, VGS=10 V
(see Figure 13)
-
15
46
-
ns
ns
26 ns
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
ISD
ISDM
VSD(1)
trr
Qrr
IRRM
trr
Qrr
IRRM
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 2.8 A, VGS=0
ISD= 2.8 A, VDD= 60 V
di/dt = 100 A/µs,
(see Figure 15)
ISD= 2.8 A,VDD= 60 V
di/dt=100 A/µs,
Tj=150 °C
(see Figure 15)
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
Min. Typ. Max. Unit
2.8 mA
-
11.2 A
- 1.5 V
220
- 1600
14
ns
nC
A
280
- 2100
15
ns
nC
A
Note:
Table 8. Gate-source Zener diode
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
BVGSO Gate-source breakdown voltage Igs ± 1mA, (open drain) 30
-
V
The built-in back- to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
For the P-channel Power MOSFETs actual polarity of voltages and current has to be
reversed.
Doc ID 18280 Rev 2
5/15
5 Page 
STD3PK50Z
Figure 16. DPAK (TO-252) drawing
Package mechanical data
Figure 17. DPAK footprint(a)
6.7
6.7
1.8 3 1.6
2.3
2.3
1.6
0068772_H
AM08850v1
a. All dimensions are in millimeters
Doc ID 18280 Rev 2
11/15
11 Page | ||
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