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PDF MT29F32G08CBAAA Data sheet ( Hoja de datos )
| Número de pieza | MT29F32G08CBAAA | |
| Descripción | NAND Flash Memory | |
| Fabricantes | Micron | |
| Logotipo |  |
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Micron Confidential and Proprietary
Advance‡
32Gb, 64Gb, 128Gb: NAND Flash
Features
NAND Flash Memory
MT29F32G08MAA ES, MT29F32G08CBAAA, MT29F64G08CFAAA,
MT29F64G08CEAAA, MT29F128G08TAA ES, MT29F128G08CJAAA,
MT29F128G08CKAAA
Features
• Open NAND Flash Interface (ONFI) 2.0-compliant
• Multilevel cell (MLC) technology
• Organization
Page size: x8: 4314 bytes (4096 + 218 bytes)
– Block size: 128 pages (512K + 27K bytes)
– Plane size: 4096 blocks
– Device size: 32Gb, 8192 blocks; 64Gb, 16,384
blocks; 128Gb, 32,768 blocks
• READ performance
– Random read: 50µs
– Sequential read: 20ns
• PROGRAM performance
– Page program: 900µs (TYP)
– Block erase: 3ms (TYP)
• Endurance: 10,000 PROGRAM/ERASE cycles1
• First block (block address 00h) guaranteed to be
valid with ECC when shipped from factory1
• Industry-standard basic NAND Flash command set
• Advanced command set
– PROGRAM PAGE CACHE MODE
– PAGE READ CACHE MODE
– Two-plane commands
– Interleaved die operations
– READ UNIQUE ID
• Operation status byte provides a software method of
detecting:
– Operation completion
– Pass/fail condition
– Write-protect status
• Ready/busy# (R/B#) signal provides a hardware
method of detecting PROGRAM and ERASE cycle
completion
• WP# signal: entire-device hardware write protect
• RESET required as first command after power-up
• INTERNAL DATA MOVE operations supported
within the plane from which data is read
Figure 1: 48-Pin TSOP Type 1
Options
• Density2: 32Gb, 64Gb, 128Gb
• Device width: x8
• Configuration:
# of die # of CE# # of R/B# I/O
TSOP
11
1 Common
TSOP
22
2 Common
TSOP
42
2 Common
LGA
22
2 Separate
LGA
42
2 Separate
• Vcc: 2.7V–3.6 V
• Package: 48-pin TSOP type I (lead-free plating),
52-pad LGA
• Operating temperature:
– Commercial temperature (0°C to +70°C)
– Extended temperature (–40°C to +85°C)
Notes: 1. For details, see “Error Management” on
page 89.
2. For part numbering and markings, see
Figure 2 on page 2.
PDF: 09005aef8331b189 / Source: 09005aef8331b1c4
32gb_nand_mlc_l63a__1.fm - Rev. A 12/08 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
1 page  
Micron Confidential and Proprietary
Advance
32Gb, 64Gb, 128Gb: NAND Flash
Table of Contents
RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
RESET FFh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
WRITE PROTECT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Interleaved Die Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Interleaved PAGE READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Interleaved TWO-PLANE PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Interleaved PROGRAM PAGE Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Interleaved PROGRAM PAGE CACHE MODE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Interleaved TWO-PLANE PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Interleaved READ for INTERNAL DATA MOVE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Interleaved TWO-PLANE READ for INTERNAL DATA MOVE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Interleaved PROGRAM for INTERNAL DATA MOVE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Interleaved TWO-PLANE PROGRAM for INTERNAL DATA MOVE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Interleaved BLOCK ERASE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Interleaved TWO-PLANE BLOCK ERASE Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Vcc Power-Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
TSOP Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
VLGA Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
PDF: 09005aef8331b189 / Source: 09005aef8331b1c4
32gb_nand_mlc_l63aTOC.fm - Rev. A 12/08 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
5 Page 
Micron Confidential and Proprietary
Advance
32Gb, 64Gb, 128Gb: NAND Flash
General Description
Figure 5: Pad Assignment (Top View) 52-Pad LGA
CE4#2
A
1234
CE3#2
CLE-1
5
CE1#
67
R/B3#2
B Vss
NC
C ALE-1
CLE-21
DNU
D
E
ALE-21
WE#-21
WE#-1
Vcc
CE2#1
RE1#
RE2#1
R/B1#
R/B2#1
F WP#-1
G I/O0-2 1
I/O0-1
Vss
WP#-2 1
I/O7-2 1
H I/O1-1
DNU/
Vss
J
K
I/O1-2 1
I/O2-1
I/O3-1
L I/O2-2 1
Vss
NC
M
Vss
N
DNU/
Vcc
NC
I/O3-2 1
I/O7-1
I/O6-1
I/O6-2 1
I/O5-1
I/O4-1
I/O5-21
Vcc
I/O4-2 1
DNU/
Vcc
R/B4#2
NC
DNU
DNU
DNU/
Vss
NC
Top View, Pads Down
Notes:
1. These pads are available only on the 64Gb and 128Gb devices. These pads are NC for other
configurations.
2. These pads are currently NC and are shown for future placement.
PDF: 09005aef8331b189 / Source: 09005aef8331b1c4
32gb_nand_mlc_l63a__2.fm - Rev. A 12/08 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
11 Page | ||
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