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PDF JS29F32G08AAMDB Data sheet ( Hoja de datos )
| Número de pieza | JS29F32G08AAMDB | |
| Descripción | MD332B NAND Flash Memory | |
| Fabricantes | Intel | |
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Intel® MD332B NAND Flash Memory
JS29F32G08AAMDB, JS29F64G08CAMDB, JS29F16B08JAMDB
Product Features
Preliminary Datasheet
Open NAND Flash Interface (ONFI) 2.0
Core Voltage (VCC): 2.7 V - 3.6 V
Compliant
Multilevel cell (MLC) technology
First block (block address 00h) guaranteed to
be valid when shipped from factory
Organization:
Ready/busy# (R/B#) signal provides a
— Page size: 4,320 bytes (4,096 + 224 bytes) hardware method of detecting PROGRAM or
— Block size: 256 pages (1,024K + 56K bytes) ERASE cycle completion
— Plane size: 2,048 blocks
Read performance
— Random read: 50 µs
— Sequential read: 20 ns
Write performance
WP# signal: Entire device hardware write
protect
Advanced command set:
— PAGE CACHE PROGRAM
— READ CACHE
(RANDOM, SEQUENTIAL, END)
— Page program: 900 µs (TYP)
— Multi-plane commands
— Block erase: 2 ms (TYP)
Operation status byte provides a software
Endurance:
method of detecting:
— 5,000 PROGRAM/ERASE cycles
— Operation completion
— Data Retention: JEDEC compliant
Operating Temperature:
— Pass/fail condition
— Write-protect status
— Commercial: 0°C to +70°C
— Extended: -40°C to +85°C
Density
32 Gb
64 Gb
128 Gb
Package
TSOP
TSOP
TSOP
# of Die
SDP
DDP
QDP
1
2
4
# of CE#
and R/B#
1
2
4
Bus I/O
Configuration
single x8
single x8
single x8
Device ID
89h, 68h, 04h, 46h, A9h
89h, 68h, 04h, 46h, A9h
89h, 68h, 04h, 46h, A9h
Intel Confidential
Document Number: 320844-002US
May 2009
1 page  
Intel® MD332B NAND Flash Memory
1.0
1.1
Overview
NAND Flash technology provides a cost-effective solution for applications requiring
high-density solid-state storage for:
• 32 Gb NAND Flash memory device
• 64 Gb two-die stack that operates as two independent 32 Gb devices
• 128 Gb four-die stacks that operates as four independent 32 Gb devices
Intel® NAND Flash devices include standard NAND Flash features as well as new
features designed to enhance system-level performance.
Architecture
Intel NAND Flash devices use a highly multiplexed 8-bit bus (I/O[7:0]) to transfer data,
addresses, and instructions. The five command pins (CLE, ALE, CE#, RE#, WE#)
implement the NAND Flash command bus interface protocol. Two additional pins control
hardware write protection (WP#) and monitor device status (R/B#).
This hardware interface creates a low-pin-count device with a standard pinout that is
the same from one density to another, allowing future upgrades to higher densities
without board redesign.
The 32 Gb device contain two planes in a single die. Each plane consists of 2,048
blocks. Each block is subdivided into 256 programmable pages. Each page consists of
4,320 bytes. The pages are further divided into a 4,096-byte data storage region with a
separate 224-byte area. The 224-byte area is typically used for error management
functions.
The 64 Gb and 128 Gb devices are created by stacking 32 Gb memory.
The contents of each 4,320-byte page can be programmed in 900 µs, and an entire
block can be erased in 2 ms. On-chip control logic automates PROGRAM and ERASE
operations to maximize cycle endurance. ERASE/PROGRAM endurance is specified at
5,000 cycles when using appropriate error correcting code (ECC) and error
management.
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
This provides a memory device with a low pin count. The commands received at the
I/O control circuits are latched by a command register and are transferred to control
logic circuits for generating internal signals to control device operations. The addresses
are latched by an address register and sent to a row decoder or a column decoder to
select a row address or a column address, respectively.
The data are transferred to or from the NAND Flash memory array, byte by byte (x8),
through a data register and a cache register. The cache register is closest to I/O control
circuits and acts as a data buffer for the I/O data, whereas the data register is closest
to the memory array and acts as a data buffer for the NAND Flash memory array
operation.
May 2009
Document Number: 320844-002US
Intel Confidential
Intel® MD332B NAND Flash Memory
Preliminary Datasheet
5
5 Page 
Intel® MD332B NAND Flash Memory
Figure 6. QDP TSOP Configuration
CE#
CLE
ALE
WE#
RE#
I/O[7:0]
WP#
Target 1
LUN 1
CE2#
CLE
ALE
WE#
RE#
I/O[7:0]
WP#
Target 2
LUN 1
CE3#
CLE
ALE
WE#
RE#
I/O[7:0]
WP#
Target 3
LUN 1
CE4#
CLE
ALE
WE#
RE#
I/O[7:0]
WP#
Target 4
LUN 1
JS29F16B08JAMDB Device
R/B#
R/B2#
R/B3#
R/B4#
May 2009
Document Number: 320844-002US
Intel Confidential
Intel® MD332B NAND Flash Memory
Preliminary Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet JS29F32G08AAMDB.PDF ] | |
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