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24C08 데이터시트 PDF




Bookly Micro에서 제조한 전자 부품 24C08은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 24C08 기능
기능 2-WIRE SERIAL CMOS EEPROM
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24C08 데이터시트, 핀배열, 회로
24C02 24C04
24C08 24C16
ISBookly Micro
1K-bit/2K-bit/4K-bit/8K-bit/16K-bit
2-WIRE SERIAL CMOS EEPROM
JANUARY 20077
FEATURES
• Two-Wire Serial Interface, I2CTM Compatible
–Bi-directional data transfer protocol
• Wide Voltage Operation
–Vcc = 1.8V to 5.5V
• 400 KHz (2.5V) and 1 MHz (5.0V) Compatible
• Low Power CMOS Technology
–Standby Current less than 6 µA (5.0V)
–Read Current less than 2 mA (5.0V)
–Write Current less than 3 mA (5.0V)
• Hardware Data Protection
–Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
5 ms max @ 2.5V
• Organization:
–24C02, 256x8 (one block of 256 bytes)
–24C04, 512x8 (two blocks of 256 bytes)
–24C08, 1024x8 (four blocks of 256 bytes)
–24C16, 2048x8 (eight blocks of 256 bytes)
• 16 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 100 Years
Replace Atmel /Microchip /Philips / FM 24C
or 24LC02/04/08/16 without change anything
• 8-pin PDIP, 8-pin SOIC, 8-pad DFN, 8-pin
TSSOP, and 8-pin MSOP packages
Designed with Samsung technology
DESCRIPTION
The 24C02, 24C04, 24C08, and
24C16 are electrically erasable PROM
devices that use the standard 2-wire interface for
communications. The 24C02, 24C04,
24C08, and 24C16 contain a memory array
of 2K-bits (256 x 8), 4K-bits (512 x 8), 8K-bits
(1,024 x 8), and 16K-bits (2,048 x 8), respectively.
Each device is organized into 16 byte pages for
page write mode.
This EEPROM operates in a wide voltage range of
1.8V to 5.5V to be compatible with most application
voltages. BM designed this device family to be a
practical, low-power 2-wire EEPROM solution. The
devices are available in 8-pin PDIP, 8-pin SOIC, 8-
pad DFN, 8-pin MSOP, and 8-pin TSSOP pack-
ages. Replace Atmel or Microchip 24xx directly.
The 24C02/04/08/16 maintains compatibil-
ity with the popular 2-wire bus protocol, so it is
easy to use in applications implementing this bus
type. The simple bus consists of the Serial Clock
wire (SCL) and the Serial Data wire (SDA). Using
the bus, a Master device such as a microcontroller
is usually connected to one or more Slave devices
such as this device. The bit stream over the SDA
line includes a series of bytes, which identifies a
particular Slave device, an instruction, an address
within that Slave device, and a series of data, if
appropriate. The 24C02/04/08/16 has a
Write Protect pin (WP) to allow blocking of any
write instruction transmitted over the bus.
Copyright © 2007 Bookly Micro Electronics, Inc. All rights reserved. BM reserves the right to make changes to this specification and its products at any time
without notice. BM assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www. bookly .com 1-800-379-4774
Rev. F
01/09/06




24C08 pdf, 반도체, 판매, 대치품
24C02 24C04 24C08 24C16
BM®
DEVICE OPERATION
24C02/04/08/16 features serial communication and
supports a bi-directional 2-wire bus transmission protocol
called I2CTM.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device that
sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by
Master device that generates the SCL, controls the bus
access, and generates the Stop and Start conditions. The
24C02/04/08/16 is the Slave device on the bus.
The Bus Protocol:
– Data transfer may be initiated only when the bus is not busy
– During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA
line while the SCL line is high will be interpreted as a Start
or Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of the
High period of the clock signal. The data on the SDA line may
be changed during the Low period of the clock signal. There
is one clock pulse per bit of data. Each data transfer is
initiated with a Start condition and terminated with a Stop
condition.
Start Condition
The Start condition precedes all commands to the device and
is defined as a High to Low transition of SDA when SCL is High.
The EEPROM monitors the SDA and SCL lines and will
not respond until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with
a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The 24C02/04/08/16 contains a reset function
in case the 2-wire bus transmission is accidentally
interrupted (eg. a power loss), or needs to be
terminated mid-stream. The reset is caused when the
Master device creates a Start condition. To do this, it
may be necessary for the Master device to monitor the
SDA line while cycling the SCL up to nine times. (For
each clock signal transition to High, the Master checks
for a High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The
24C02/04/08/16 will enter standby mode: a) At
Power-up, and remain in it until SCL or SDA toggles; b)
Following the Stop signal if a no write operation is
initiated; or c) Following any internal write operation.
4 www.bookly.com

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24C08 전자부품, 판매, 대치품
24C02 24C04 24C08 24C16
FIGURE 1. TYPICAL SYSTEM BUS CONFIGURATION
SDA
SCL
Vcc
Master
Transmitter/
Receiver
24Cxx
BM ®
FIGURE 2. OUTPUT ACKNOWLEDGE
SCL from
Master
1
Data Output
from
Transmitter
Data Output
from
Receiver
FIGURE 3. START AND STOP CONDITIONS
SCL
SDA
89
tAA tAA
ACK
Rev. F
01/09/06
www.bookly.com
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