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GAL26CLV12D-7LJ 데이터시트 PDF




Lattice Semiconductor에서 제조한 전자 부품 GAL26CLV12D-7LJ은 전자 산업 및 응용 분야에서
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부품번호 GAL26CLV12D-7LJ 기능
기능 Low Voltage E2CMOS PLD Generic Array Logic
제조업체 Lattice Semiconductor
로고 Lattice Semiconductor 로고


GAL26CLV12D-7LJ 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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GAL26CLV12D-7LJ 데이터시트, 핀배열, 회로
GAL26CLV12
Low Voltage E2CMOS PLD
Generic Array Logic™
FFEeAaTtUuRrEeSs
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 200 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— Inputs and I/O Interface with Standard 5V TTL Devices
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram
I/CLK
I
I
I
I
I
I
I
I
I
I
I
I
RESET
8
OLMC
8
OLMC
8
OLMC
8
OLMC
10
OLMC
12
OLMC
12
OLMC
10
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
PRESET
INPUT
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Description
The GAL26CLV12D, at 5 ns maximum propagation delay time,
provides higher performance than its 5V counterpart. The
GAL26CLV12D can interface with both 3.3V and 5V signal levels.
The GAL26CLV12D is manufactured using Lattice Semiconductor's
advanced 3.3V E2CMOS process, which combines CMOS with
Electrically Erasable (E2) floating gate technology. High speed erase
times (<100ms) allow the devices to be reprogrammed quickly and
efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
PLCC
4 2 28 26
I
I
VCC
I
I
I
I
5 25
7 GAL26CLV12D 23
Top View
9 21
11 19
12 14 16 18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
26clv12_02
1




GAL26CLV12D-7LJ pdf, 반도체, 판매, 대치품
Registered Mode
AR
DQ
CLK
Q
SP
S =0
0
S1 = 0
ACTIVE LOW
Combinatorial Mode
Specifications GAL26CLV12
AR
DQ
CLK
Q
SP
S =1
0
S1 = 0
ACTIVE HIGH
S =0
0
S1 = 1
ACTIVE LOW
S =1
0
S1 = 1
ACTIVE HIGH
4

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GAL26CLV12D-7LJ 전자부품, 판매, 대치품
Specifications GAL26CLV12
AC Switching Characteristics
Over Recommended Operating Conditions
TEST
PARAMETER COND1.
DESCRIPTION
tpd2 A Input or I/O to Combinational Output
tco2 A Clock to Output Delay
tcf3 Clock to Feedback Delay
tsu Setup Time, Input or Feedback before Clock
th Hold Time, Input or Feedback after Clock
fmax4
A Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with
No Feedback
twh4
Clock Pulse Duration, High
twl4 Clock Pulse Duration, Low
ten B Input or I/O to Output Enabled
tdis C Input or I/O to Output Disabled
tar A Input or I/O to Asynchronous Reset of Register
tarw
Asynchronous Reset Pulse Duration
tarr Asynchronous Reset to ClockRecovery Time
tspr Synchronous Preset to ClockRecovery Time
1) Refer to Switching Test Conditions section.
2) Minimum values for tpd and tco are not 100% tested but established by characterization.
3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
4) Refer to fmax Descriptions section. Characterized but not 100% tested.
COM
COM
-5 -7
UNITS
MIN. MAX. MIN. MAX.
1 5 1 7.5 ns
1 3.5 1 4.5 ns
3 3 ns
3.5 5.5 ns
0 0 ns
143 100 MHz
154 117 MHz
200 142 MHz
2.5 3.5
2.5 3.5
1 6 1 7.5
1 6 1 7.5
16 1 9
5.5 7
45
45
ns
ns
ns
ns
ns
ns
ns
ns
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
CI
CI/O
PARAMETER
Input Capacitance
I/O Capacitance
TYPICAL
8
8
UNITS
pF
pF
TEST CONDITIONS
VCC = 3.3V, VI = 0V
VCC = 3.3V, VI/O = 0V
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GAL26CLV12D-7LJ

Low Voltage E2CMOS PLD Generic Array Logic

Lattice Semiconductor
Lattice Semiconductor

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