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AT30TS74 데이터시트 PDF




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부품번호 AT30TS74 기능
기능 Digital Temperature Sensor
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AT30TS74 데이터시트, 핀배열, 회로
AT30TS74
9- to 12-bit Selectable, ±1.0°C Accurate
Digital Temperature Sensor
PRELIMINARY DATASHEET
Features
Single 1.7V to 5.5V Supply
Measures Temperature From -55C to +125C
Highly Accurate Temperature Measurements Requiring No External
Components
̶ ±1.0C Accuracy (Typical) Over the -20C to +100C Range
̶ ±1.0C Accuracy (Typical) Over the -10C to +100C Range (WLCSP Only)
̶ ±2.0C Accuracy (Typical) Over the -40C to +125C Range
User-configurable Resolution
̶ 9 to 12 bits (0.5C to 0.0625C)
User-configurable High and Low Temperature Limits
ALERT Output Pin for Indicating Temperature Alarms
2-Wire I2C and SMBusCompatible Serial Interface
̶ Supports SMBus Timeout
̶ Supports SMBus Alert and Alert Response Address (ARA)
̶ Selectable Addressing Allows Up to Eight Devices on the Same Bus
I2C High-Speed (HS) Mode Compatible
̶ 3.4MHz Maximum Clock Frequency
Built-in noise Suppression Filtering for Clock and Data Input Signals
Low-power Dissipation
̶ 85μA Active Current (Typical) During Temperature Measurements
Shutdown Mode to Minimize Power Consumption
̶ 1μA Shutdown Current (Typical)
One-Shot Mode for Single Temperature Measurement While in Shutdown
Mode
Pin and Software Compatible to Industry-standard LM75-type Devices
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
̶ 8-lead SOIC (150mil)
̶ 8-lead MSOP (3.0 x 3.0mm)
̶ 8-pad Ultra Thin DFN (UDFN — 2.0 x 3.0 x 0.6mm)
̶ 4-ball WLCSP
Atmel-8897D-DTS-AT30TS74-Datasheet_102014




AT30TS74 pdf, 반도체, 판매, 대치품
8. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.1 Atmel Ordering Code Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.2 Green Package Options (Pb/Halide-free/RoHS Compliant) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9. Part Marking Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.1 8S1 — 8-lead JEDEC SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.2 8XM — 8-lead MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.3 8MA2 — 8-pad UDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.4 4U-3 — 4-ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11.1 No Errata. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4 AT30TS74 [PRELIMINARY DATASHEET]
Atmel-8897D-DTS-AT30TS74-Datasheet_102014

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AT30TS74 전자부품, 판매, 대치품
3. Device Communication
The AT30TS74 operates as a slave device and utilizes a simple 2-Wire I2C and SMBus compatible digital serial
interface to communicate with a host controller, commonly referred to as the bus Master. The Master initiates
and controls all Read and Write operations to the slave devices on the serial bus, and both the Master and the
slave devices can transmit and receive data on the bus.
The serial interface is comprised of just two signal lines:
Serial Clock (SCL):
The SCL pin is used to receive the clock signal from the Master.
Serial Data (SDA):
The bidirectional SDA pin is used to receive command and data information from the Master as well as to
send data back to the Master.
Data is always latched into the AT30TS74 on the rising edge of SCL and always output from the device on the
falling edge of SCL. Both the SCL and SDA pin incorporate integrated spike suppression filters and Schmitt
Triggers to minimize the effects of input spikes and bus noise.
All command and data information is transferred with the Most-Significant Bit (MSB) first. During bus
communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data has been
transferred, the receiving device must respond with either an Acknowledge (ACK) or a No-acknowledge (NACK)
response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by the Master. Therefore, nine clock
cycles are required for every one byte of data transferred. There are no unused clock cycles during any Read or
Write operation, so there must not be any interruptions or breaks in the data stream during each data byte
transfer and ACK or NACK clock cycle.
During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable
while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will
occur. Start and Stop conditions are used to initiate and end all serial bus communication between the Master
and the slave devices. The number of data bytes transferred between a Start and a Stop condition is not limited
and is determined by the Master.
In order for the serial bus to be idle, both the SCL and SDA pins must be in the logic-high state at the same time.
3.1 Start Condition
A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is stable in the
logic-high state. The Master uses a Start condition to initiate any data transfer sequence, and the Start condition
must precede any command. The AT30TS74 will continuously monitor the SDA and SCL pins for a Start
condition, and the device will not respond unless one is given.
3.2 Stop Condition
A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the
logic-high state. The Master uses the Stop condition to end a data transfer sequence to the AT30TS74 which
will subsequently return to the idle state. The Master can also utilize a repeated Start condition instead of a Stop
condition to end the current data transfer if the Master will perform another operation.
3.3 Acknowledge (ACK)
After every byte of data received, the AT30TS74 must acknowledge to the Master it has successfully received
the data byte by responding with an ACK. This is accomplished by the Master first releasing the SDA line and
providing the ACK/NACK clock cycle (a ninth clock cycle for every byte). During the ACK/NACK clock cycle, the
AT30TS74 must output a Logic 0 (ACK) for the entire clock cycle such that the SDA line must be stable in the
logic-low state during the entire high period of the clock cycle.
AT30TS74 [PRELIMINARY DATASHEET]
Atmel-8897D-DTS-AT30TS74-Datasheet_102014
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
AT30TS74

Digital Temperature Sensor

ATMEL Corporation
ATMEL Corporation
AT30TS75

Digital Temperature Sensor

ATMEL Corporation
ATMEL Corporation

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