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GAL6002B-20LJ 데이터시트 PDF




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부품번호 GAL6002B-20LJ 기능
기능 High Performance E2CMOS FPLA Generic Array Logic
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GAL6002B-20LJ 데이터시트, 핀배열, 회로
GAL6002
High Performance E2CMOS FPLA
Generic Array Logic™
Features
Functional Block Diagram
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
15ns Maximum Propagation Delay
75MHz Maximum Frequency
6.5ns Maximum Clock to Output Delay
TTL Compatible 16mA Outputs
UltraMOS® Advanced CMOS Technology
ACTIVE PULL-UPS ON ALL PINS
INPUT
CLOCK
{INPUTS
2-11
ICLK
2
11
ILMC
AND
OUTPUT
ENABLE
14
23
IOLMC
LOW POWER CMOS
90mA Typical Icc
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
UNPRECEDENTED FUNCTIONAL DENSITY
78 x 64 x 36 FPLA Architecture
10 Output Logic Macrocells
8 Buried Logic Macrocells
20 Input and I/O Logic Macrocells
HIGH-LEVEL DESIGN FLEXIBILITY
Asynchronous or Synchronous Clocking
Separate State Register and Input Clock Pins
Functional Superset of Existing 24-pin PAL®
and FPLA Devices
APPLICATIONS INCLUDE:
Sequencers
State Machine Control
Multiple PLD Device Integration
Description
0
7
BLMC
D
E
OR
Macrocell Names
14
D 23
OLMC
E
OCLK
ILMC INPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
BLMC BURIED LOGIC MACROCELL
OLMC OUTPUT LOGIC MACROCELL
{ OUTPUTS
14 - 23
OUTPUT
CLOCK
PinNames
I0 - I10
ICLK
OCLK
INPUT
INPUT CLOCK
OUTPUT CLOCK
I/O/Q
V
CC
GND
BIDIRECTIONAL
POWER (+5V)
GROUND
Having an FPLA architecture, the GAL6002 provides superior
flexibility in state-machine design. The GAL6002 offers the highest
degree of functional integration, flexibility, and speed currently
available in a 24-pin, 300-mil package. E2CMOS technology offers
high speed (<100ms) erase times, providing the ability to reprogram
or reconfigure the device quickly and efficiently.
The GAL6002 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
4
I5
2 28 26
25 I/O/Q
I I/O/Q
I7
23 I/O/Q
NC GAL6002 NC
I 9 Top View 21 I/O/Q
I I/O/Q
I 11
19 I/O/Q
12 14 16 18
DIP
I/ICLK 1
I
24 Vcc
I/O/Q
I
I GAL
I 6002
I/O/Q
I/O/Q
I/O/Q
I6
I/O/Q
I 18 I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
GND 12
13 OCLK
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
6002_02
1




GAL6002B-20LJ pdf, 반도체, 판매, 대치품
ILMC and IOLMC Configurations
ICLK
Specifications GAL6002
INPUT
or I/O
LATCH
E
Q
D
INVALID
REG.
Q
D
MUX
00
01
10
11
AND
ARRAY
LATCH(i) ISYN(i)
ILMC/IOLMC
Generic Logic Block Diagram
Input Macrocell JEDEC Fuse Numbers
INSYNC
8218
8220
8222
8224
8226
8228
8230
8232
8234
8236
INLATCH
8219
8221
8223
8225
8227
8229
8231
8233
8235
8237
ILMC
0
1
2
3
4
5
6
7
8
9
I/O Macrocell JEDEC Fuse Numbers
IOSYNC
8238
8240
8242
8244
8246
8248
8250
8252
8254
8256
IOLATCH
8239
8241
8243
8245
8247
8249
8251
8253
8255
8257
IOLMC
9
8
7
6
5
4
3
2
1
0
4

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GAL6002B-20LJ 전자부품, 판매, 대치품
Logic Diagram (Continued)
Specifications GAL6002
7

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