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PDF PCA9691 Data sheet ( Hoja de datos )
| Número de pieza | PCA9691 | |
| Descripción | 8-bit A/D and D/A converter | |
| Fabricantes | NXP Semiconductors | |
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PCA9691
8-bit A/D and D/A converter
Rev. 02 — 27 January 2010
Product data sheet
1. General description
The PCA9691 is a single chip, single supply, low power, 8-bit CMOS1 data acquisition
device with four analog inputs, one analog output and a serial I2C-bus interface. Three
address pins (A0, A1, and A2) are used for programming the hardware address, allowing
the use of up to 64 PCA9691 devices connected to the I2C-bus without additional
hardware. Address, control and data to and from the PCA9691 are transferred via the
serial two-line bidirectional I2C-bus.
The functions of the PCA9691 include:
• Analog input multiplexing
• On-chip sample and hold
• 8-bit Analog-to-Digital (A/D) conversion
• 8-bit Digital-to-Analog (D/A) conversion
The maximum conversion rate is given by the maximum frequency of the I2C-bus.
2. Features
8-bit successive approximation A/D conversion
Four analog inputs programmable as single-ended or differential inputs
64 different addresses by three hardware address pins
1 MHz Fast-mode Plus (Fm+) I2C-bus via serial input/output
Sampling rate given by I2C-bus frequency
Single supply voltage; operating from 2.5 V to 5.5 V
Low standby current
Analog voltage from VSS to VDD
Multiplying Digital-to-Analog Converter (DAC) with one analog output
On-chip sample and hold circuit
Auto-incremented channel selection
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 14.
1 page  
NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
7.1.1 Address map
Table 4. PCA9691 address map
Pin Bit
A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W
VSS VSS SDA 0 1 0 0 0 0 0 0
VSS VDD SDA 0 1 0 0 0 0 1 0
VDD VSS SDA 0 1 0 0 0 1 0 0
VDD VDD SDA 0 1 0 0 0 1 1 0
VSS SDA VSS 0 1 0 0 1 0 0 0
VSS SDA VDD 0 1 0 0 1 0 1 0
VDD SDA VSS 0 1 0 0 1 1 0 0
VDD SDA VDD 0 1 0 0 1 1 1 0
SDA VSS VSS 0 1 0 1 0 0 0 0
SDA VSS VDD 0 1 0 1 0 0 1 0
SDA VDD VSS 0 1 0 1 0 1 0 0
SDA VDD VDD 0 1 0 1 0 1 1 0
VSS SDA SDA 0 1 0 1 1 0 0 0
VDD SDA SDA 0 1 0 1 1 0 1 0
SDA VSS SDA 0 1 0 1 1 1 0 0
SDA VDD SDA 0 1 0 1 1 1 1 0
SDA SDA VSS 0 1 1 0 0 0 0 0
SDA SDA VDD 0 1 1 0 0 0 1 0
SDA SDA SDA 0 1 1 0 0 1 0 0
SCL SCL SCL 0 1 1 0 0 1 1 0
VSS VSS SCL 0 1 1 0 1 0 0 0
VSS VDD SCL 0 1 1 0 1 0 1 0
VDD VSS SCL 0 1 1 0 1 1 0 0
VDD VDD SCL 0 1 1 0 1 1 1 0
VSS SCL VSS 0 1 1 1 0 0 0 0
VSS SCL VDD 0 1 1 1 0 0 1 0
VDD SCL VSS 0 1 1 1 0 1 0 0
VDD SCL VDD 0 1 1 1 0 1 1 0
SCL VSS VSS 0 1 1 1 1 0 0 0
SCL VSS VDD 0 1 1 1 1 0 1 0
SCL VDD VSS 0 1 1 1 1 1 0 0
SCL VDD VDD 0 1 1 1 1 1 1 0
VSS SCL SCL 1 0 0 0 0 0 0 0
VDD SCL SCL 1 0 0 0 0 0 1 0
SCL VSS SCL 1 0 0 0 0 1 0 0
SCL VDD SCL 1 0 0 0 0 1 1 0
SCL SCL VSS 1 0 0 0 1 0 0 0
SCL SCL VDD 1 0 0 0 1 0 1 0
Address Number
40h 1
42h 2
44h 3
46h 4
48h 5
4Ah 6
4Ch 7
4Eh 8
50h 9
52h 10
54h 11
56h 12
58h 13
5Ah 14
5Ch 15
5Eh 16
60h 17
62h 18
64h 19
66h 20
68h 21
6Ah 22
6Ch 23
6Eh 24
70h 25
72h 26
74h 27
76h 28
78h 29
7Ah 30
7Ch 31
7Eh 32
80h 33
82h 34
84h 35
86h 36
88h 37
8Ah 38
PCA9691_2
Product data sheet
Rev. 02 — 27 January 2010
© NXP B.V. 2010. All rights reserved.
5 of 31
5 Page 
NXP Semiconductors
PCA9691
8-bit A/D and D/A converter
The new AOUT value is valid, at the latest, after 8.0 μs so before the rising edge of the 8th
bit of the next transferred byte. Therefore, at the full speed of the I2C-bus, the analog
output is valid under all circumstances between the rising edges of the 8th bit and the
acknowledge bit.
SCL
678A12345678A12
< 18Tosc
valid
> 8Tosc
ts(DAC)
VAOUT
Fig 10. D/A conversion sequence, example of worst case
001aag470
7.4 A/D conversion
The A/D Converter (ADC) makes use of the successive approximation conversion
technique. The on-chip DAC and a high-gain comparator are used temporarily during an
A/D conversion cycle.
An A/D conversion cycle is always started after sending a valid read mode address to a
PCA9691. The A/D conversion cycle is triggered at the trailing edge of the acknowledge
clock pulse and is executed while transmitting the result of the previous conversion (see
Figure 11).
protocol S
ADDRESS
1A
DATA BYTE 0
A
DATA BYTE 1
A
DATA BYTE 2
A
SCL
12
891
91
91
SDA
sampling byte 1
sampling byte 2
sampling byte 3
Fig 11. A/D conversion sequence
conversion of byte 1
transmission
of previously
converted byte
conversion of byte 2
transmission
of byte 1
conversion of byte 3
transmission
of byte 2
mbl829
Once a conversion cycle is triggered, an input voltage sample of the selected channel is
stored on the chip and is converted to the corresponding 8-bit binary code. Samples
picked up from differential inputs are converted to an 8-bit two’s complement code (see
Figure 12 and Figure 13).
The conversion result is stored in the ADC data register and awaits transmission. If the
auto-increment flag is set the next channel is selected.
PCA9691_2
Product data sheet
Rev. 02 — 27 January 2010
© NXP B.V. 2010. All rights reserved.
11 of 31
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