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PDF PCA8574 Data sheet ( Hoja de datos )
| Número de pieza | PCA8574 | |
| Descripción | Remote 8-bit I/O expander | |
| Fabricantes | NXP Semiconductors | |
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PCA8574; PCA8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Rev. 3 — 3 June 2013
Product data sheet
1. General description
The PCA8574/74A provides general-purpose remote I/O expansion via the two-wire
bidirectional I2C-bus (serial clock (SCL), serial data (SDA)).
The devices consist of eight quasi-bidirectional ports, 400 kHz I2C-bus interface, three
hardware address inputs and interrupt output operating between 2.3 V and 5.5 V. The
quasi-bidirectional port can be independently assigned as an input to monitor interrupt
status or keypads, or as an output to activate indicator devices such as LEDs. The system
master can read from the input port or write to the output port through a single register.
The low current consumption of 4.5 A (typical, static) is great for mobile applications and
the latched output ports have 25 mA high current sink drive capability for directly driving
LEDs.
The PCA8574 and PCA8574A are identical, except for the different fixed portion of the
slave address. The three hardware address pins allow eight of each device to be on the
same I2C-bus, so there can be up to 16 of these I/O expanders PCA8574/74A together on
the same I2C-bus, supporting up to 128 I/Os (for example, 128 LEDs).
The active LOW open-drain interrupt output (INT) can be connected to the interrupt logic
of the microcontroller and is activated when any input state differs from its corresponding
input port register state. It is used to indicate to the microcontroller that an input state has
changed and the device needs to be interrogated without the microcontroller continuously
polling the input register via the I2C-bus.
The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal
pull-up 100 A current source.
2. Features and benefits
I2C-bus to parallel port expander
400 kHz I2C-bus interface (Fast-mode I2C-bus)
Operating supply voltage 2.3 V to 5.5 V with 5.5 V tolerant I/Os held to VDD with
100 A current source
8-bit remote I/O pins that default to inputs at power-up
Latched outputs with 25 mA sink capability for directly driving LEDs
Total package sink capability of 200 mA
Active LOW open-drain interrupt output
Eight programmable slave addresses using three address pins
Low standby current (4.5 A typical)
40 C to +85 C operation
1 page  
NXP Semiconductors
PCA8574; PCA8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
6.2 Pin description
Table 3.
Symbol
A0
A1
A2
P0
P1
P2
P3
VSS
P4
P5
P6
P7
INT
SCL
SDA
VDD
n.c.
Pin description
Pin Description
DIP16, SO16 SSOP20
1 6 address input 0
2 7 address input 1
3 9 address input 2
4 10 quasi-bidirectional I/O 0
5 11 quasi-bidirectional I/O 1
6 12 quasi-bidirectional I/O 2
7 14 quasi-bidirectional I/O 3
8 15 supply ground
9 16 quasi-bidirectional I/O 4
10 17 quasi-bidirectional I/O 5
11 19 quasi-bidirectional I/O 6
12 20 quasi-bidirectional I/O 7
13 1 interrupt output (active LOW)
14 2 serial clock line
15 4 serial data line
16 5 supply voltage
- 3, 8, 13, 18 not connected
7. Functional description
Refer to Figure 1 “Block diagram”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address format of the
PCA8574/74A is shown in Figure 6. Slave address pins A2, A1 and A0 are held HIGH or
LOW to choose one of eight slave addresses. To conserve power, no internal pull-up
resistors are incorporated on pins A2, A1, or A0 so they must be externally held HIGH or
LOW. The address pins (A2, A1, A0) can connect to VDD or VSS directly or through
resistors.
PCA8574_PCA8574A
Product data sheet
slave address
R/W
slave address
R/W
0 1 0 0 A2 A1 A0 0
0 1 1 1 A2 A1 A0 0
fixed
hardware
selectable
002aah469
fixed
hardware
selectable
002aah470
a. PCA8574
b. PCA8574A
Fig 6. PCA8574 and PCA8574A slave addresses
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 3 June 2013
© NXP B.V. 2013. All rights reserved.
5 of 32
5 Page 
NXP Semiconductors
PCA8574; PCA8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
9. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-wire communication between different ICs or modules. The
two wires are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 11).
SDA
SCL
Fig 11. Bit transfer
data line
stable;
data valid
change
of data
allowed
mba607
9.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 12).
SDA
SCL
S
START condition
Fig 12. Definition of START and STOP conditions
P
STOP condition
mba608
9.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 13).
PCA8574_PCA8574A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 3 June 2013
© NXP B.V. 2013. All rights reserved.
11 of 32
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