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기능 16M x 16 bit DDR Synchronous DRAM
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AS4C16M16D1-5BIN 데이터시트, 핀배열, 회로
AS4C16M16D1
16M x 16 bit DDR Synchronous DRAM (SDRAM)
Alliance Memory Confidential
Advanced (Rev. 1.1, Sep. /2011)
Features
Fast clock rate: 200MHz
Differential Clock CK & CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 4M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte-write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
Precharge & active power down
Power supplies: VDD & VDDQ = 2.5V 0.2V
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
- Pb free and Halogen free
Package: 60-Ball, 8x13x1.2 mm (max) TFBGA
- Pb free and Halogen Free
Overview
The AS4C16M16D1 SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 256 Mbits.
It is internally configured as a quad 4M x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CK). Data outputs occur
at both rising edges of CK and CK .d Read and write
accesses to the SDRAM are burst oriented; accesses start
at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command
which is then followed by a Read or Write command. The
AS4C16M16D1 provides programmable Read or Write
burst lengths of 2, 4, or 8. An auto precharge function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use. In
addition, AS4C16M16D1 features programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring high
memory band-width, result in a device particularly well
suited to high performance main memory and graphics
applications.
Table 1.Ordering Information
Part Number
Clock Data Rate Package Temperature Temp Range
AS4C16M16D1-5TCN 200MHz 400Mbps/pin 66pin TSOPII Commercial 0 ~ 70°C
AS4C16M16D1-5TIN 200MHz 400Mbps/pin 66pin TSOPII Industrial -40 ~ 85°C
AS4C16M16D1-5BCN 200MHz 400Mbps/pin 60ball TFBGA Commercial 0 ~ 70°C
AS4C16M16D1-5BIN 200MHz 400Mbps/pin 60ball TFBGA Industrial -40 ~ 85°C
T: indicates TSOP II package
B: indicates TFBGA package
C: indicates Commercial temp.
I: indicates Industrial temp.
N: indicates lead free ROHS
Alliance Memory, Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory, Inc. reserves the right to change products or specification without notice.




AS4C16M16D1-5BIN pdf, 반도체, 판매, 대치품
AS4C16M16D1
Pin Descriptions
Table 2. Pin Details
Symbol
CK, CK
CKE
BA0, BA1
A0-A12
CS
RAS
CAS
WE
LDQS,
UDQS
LDM,
UDM
DQ0 - DQ15
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input /
Output
Input
Input /
Output
Description
Differential Clock: CK, CK are driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CK. Both CK and CK increment the internal burst
counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains
low. When all banks are in the idle state, deactivating the clock controls the entry to
the Power Down and Self Refresh modes.
Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs: A0-A12 are sampled during the BankActivate command (row
address A0-A12) and Read/Write command (column address A0-A8 with A10 defining
Auto Precharge).
Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS is sampled HIGH. CS
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Row Address Strobe: The RAS signal defines the operation commands in
conjunction with the CAS and WE signals and is latched at the positive edges of CK.
When RAS and CS are asserted "LOW" and CAS is asserted "HIGH," either the
BankActivate command or the Precharge command is selected by the WE signal.
When the WE is asserted "HIGH," the BankActivate command is selected and the
bank designated by BA is turned on to the active state. When the WE is asserted
"LOW," the Precharge command is selected and the bank designated by BA is
switched to the idle state after the precharge operation.
Column Address Strobe: The CAS signal defines the operation commands in
conjunction with the RAS and WE signals and is latched at the positive edges of CK.
When RAS is held "HIGH" and CS is asserted "LOW," the column access is started
by asserting CAS "LOW." Then, the Read or Write command is selected by asserting
WE "HIGH" or “LOW”.
Write Enable: The WE signal defines the operation commands in conjunction with
the RAS and CAS signals and is latched at the positive edges of CK. The WE input
is used to select the BankActivate or Precharge command and Read or Write
command.
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data
Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data
and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15.
Data Input Mask: Input data is masked when DM is sampled HIGH during a write
cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
Data I/O: The DQ0-DQ15 input and output data are synchronized with the positive
edges of CK and CK The I/Os are byte-maskable during Writes.
Alliance Memory, lnc. Confidential
4
Rev. 1.1
Sep. /2011

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AS4C16M16D1-5BIN 전자부품, 판매, 대치품
AS4C16M16D1
Mode Register Set (MRS)
The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs
CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The
default value of the Mode Register is not defined; therefore the Mode Register must be written by the user.
Values stored in the register will be retained until the register is reprogrammed. The Mode Register is written by
asserting Low on CS , RAS , CAS , WE , BA1 and BA0 (the device should have all banks idle with no bursts in
progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A12
and BA0, BA1 in the same cycle in which CS , RAS , CAS and WE are asserted Low is written into the Mode
Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the Mode
Register. The Mode Register is divided into various fields depending on functionality. The Burst Length uses
A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0
should be programmed to all the undefined addresses to ensure future compatibility. Reserved states should not
be used to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific
codes for various burst lengths, burst types and CAS latencies.
Table 4. Mode Register Bitmap
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0 0 RFU must be set to 0T.M.
CAS Latency BT Burst Length Mode Register
A8 A7 Test Mode
0 0 Normal mode
1 0 DLL Reset
X 1 Test mode
BA0 Mode
0 MRS
1 EMRS
A6 A5 A4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
010
2
011
3
1 0 0 Reserved
1 0 1 Reserved
110
2.5
1 1 1 Reserved
A3 Burst Type
0 Sequential
1 Interleave
A2 A1 A0 Burst Length
0 0 0 Reserved
001
2
010
4
011
8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be
2, 4, 8.
Table 5. Burst Length
A2 A1 A0
000
001
010
011
100
101
110
111
Burst Length
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Alliance Memory, lnc. Confidential
7
Rev. 1.1
Sep. /2011

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AS4C16M16D1-5BIN

16M x 16 bit DDR Synchronous DRAM

Alliance Semiconductor
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