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zDA14580 데이터시트 PDF




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부품번호 zDA14580 기능
기능 Low Power Bluetooth Smart SoC
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zDA14580 데이터시트, 핀배열, 회로
DATASHEET - FINAL
DA14580
Low Power Bluetooth Smart SoC
JANUARY 29, 2015 V3.1
General description
84 kB ROM
The DA14580 integrated circuit has a fully integrated
radio transceiver and baseband processor for Blue-
tooth® Smart. It can be used as a standalone applica-
tion processor or as a data pump in hosted systems.
8 kB Retention SRAM
Power management
Integrated Buck/Boost DC-DC converter
P0, P1, P2 and P3 ports with 3.3 V tolerance
Easy decoupling of only 4 supply pins
The DA14580 supports a flexible memory architecture
Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)
for storing Bluetooth profiles and custom application
battery cells
code, which can be updated over the air (OTA). The
10-bit ADC for battery voltage measurement
qualified Bluetooth Smart protocol stack is stored in a
dedicated ROM. All software runs on the ARM® Cor-
tex®-M0 processor via a simple scheduler.
Digital controlled oscillators
16 MHz crystal (±20 ppm max) and RC oscillator
32 kHz crystal (±50 ppm, ±500 ppm max) and
The Bluetooth Smart firmware includes the L2CAP ser-
vice layer protocols, Security Manager (SM), Attribute
Protocol (ATT), the Generic Attribute Profile (GATT)
and the Generic Access Profile (GAP). All profiles pub-
lished by the Bluetooth SIG as well as custom profiles
are supported.
RCX oscillator
General purpose, Capture and Sleep timers
Digital interfaces
General purpose I/Os: 14 (WLCSP34 package),
24 (QFN40 package), 32 (QFN48 package)
2 UARTs with hardware flow control up to 1 MBd
SPI+™ interface
The transceiver interfaces directly to the antenna and
I2C bus at 100 kHz, 400 kHz
is fully compliant with the Bluetooth 4.1 standard.
3-axes capable Quadrature Decoder
The DA14580 has dedicated hardware for the Link
Layer implementation of Bluetooth Smart and interface
controllers for enhanced connectivity capabilities.
Analog interfaces
4-channel 10-bit ADC
Radio transceiver
Fully integrated 2.4 GHz CMOS transceiver
Features
Single wire antenna: no RF matching or RX/TX
switching required
Complies with Bluetooth V4.1, ETSI EN 300 328 and
Supply current at VBAT3V:
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
(US) and ARIB STD-T66 (Japan)
0 dBm transmit output power
Processing power
-20 dBm output power in “Near Field Mode”
16 MHz 32 bit ARM Cortex-M0 with SWD inter-
-93 dBm receiver sensitivity
face Packages:
Dedicated Link Layer Processor
WLCSP 34 pins, 2.436 mm x 2.436 mm
AES-128 bit encryption Processor
QFN 40 pins, 5 mm x 5 mm
Memories
QFN 48 pins, 6 mm x 6 mm
32 kB One-Time-Programmable (OTP) memory
KGD (wafer, dice)
42 kB System SRAM
________________________________________________________________________________________________
System diagram
© 2014 Dialog Semiconductor
1 www.dialog-semiconductor.com




zDA14580 pdf, 반도체, 판매, 대치품
2. Pinout
The DA14580 comes in three packages:
1. A Wafer Level Chip Scale Package (WLCSP) with
34 balls
2. A Quad Flat Package No Leads (QFN) with 48 pins
3. A Quad Flat Package No Leads (QFN) with 40 pins
The actual pin/ball assignment is depicted in the follow-
ing figures:
123456
A
B
C
D
E
F
Figure 2 WLCSP34 ball assignment
P0_0
P0_1
P0_2
P0_3
P3_0
P0_4
P0_5
P2_1
P0_6
P3_1
P0_7
P3_2
1
2
3
4
5
6
7
8
9
10
11
12
Pin 0: GND plane
DA14580
(Top View)
36 P3_6
35 XTAL16Mm
34 XTAL16Mp
33 P1_3
32 P1_2
31 SW_CLK
30 SWDIO
29 P1_1
28 VBAT1V
27 P1_0
26 SWITCH
25 P3_5
Figure 3 QFN48 pin assignment
© 2014 Dialog Semiconductor 4 Final - January 29, 2015 v3.1

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zDA14580 전자부품, 판매, 대치품
Table 3: Pin Description
PIN NAME
TYPE
Drive
(mA)
QD_CHA_Z
DI
QD_CHB_Z
DI
SPI bus interface
SPI_CLK
DO
SPI_DI
DI
SPI_DO
DO
SPI_EN
DI
I2C bus interface
SDA
DIO/DIOD
SCL DIO/DIOD
UART interface
UTX
DO
URX
DI
URTS
DO
UCTS
DI
UTX2
DO
URX2
DI
URTS2
DO
UCTS2
DI
Analog interface
ADC[0]
AI
ADC[1]
AI
ADC[2]
AI
ADC[3]
AI
Radio transceiver
RFIOp
AIO
RFIOm
AIO
Miscellaneous
RST DI
VBAT_RF
VDCDC_RF
VPP
AIO
AIO
AI
Power supply
VBAT3V
AIO
Reset
state
(Note )
DESCRIPTION
INPUT. Channel A for the Z axis. Mapped on Px ports
INPUT. Channel B for the Z axis. Mapped on Px ports
INPUT/OUTPUT. SPI Clock. Mapped on Px ports
INPUT. SPI Data input. Mapped on Px ports
OUTPUT. SPI Data output. Mapped on Px ports
INPUT. SPI Clock enable (active LOW). Mapped on Px ports
INPUT/OUTPUT. I2C bus Data with open drain port. Mapped on
Px ports
INPUT/OUTPUT. I2C bus Clock with open drain port. In open
drain mode, SCL is monitored to support bit stretching by a
slave. Mapped on Px ports.
OUTPUT. UART transmit data. Mapped on Px ports
INPUT. UART receive data. Mapped on Px ports
OUTPUT. UART Request to Send. Mapped on Px ports
INPUT. UART Clear to Send. Mapped on Px ports
OUTPUT. UART 2 transmit data. Mapped on Px ports
INPUT. UART 2 receive data. Mapped on Px ports
OUTPUT. UART 2 Request to Send. Mapped on Px ports
INPUT. UART 2 Clear to Send. Mapped on Px ports
INPUT. Analog to Digital Converter input 0. Mapped on P0[0]
INPUT. Analog to Digital Converter input 1. Mapped on P0[1]
INPUT. Analog to Digital Converter input 2. Mapped on P0[2]
INPUT. Analog to Digital Converter input 3. Mapped on P0[3]
RF input/output. Impedance 50 
RF ground
INPUT. Reset signal (active high). Must be connected to GND if
not used.
Connect to VBAT3V on the PCB
Connect to VDCDC on the PCB
INPUT. This pin is used while OTP programming and testing.
OTP programming: VPP = 6.8 V ± 0.25 V
OTP Normal operation: leave VPP floating
INPUT/OUTPUT. Battery connection. Used for a single coin bat-
tery (3 V). If an alkaline or a NiMH battery (1.5 V) is attached to
pin VBAT1V, this is the second output of the DC-DC converter.
© 2014 Dialog Semiconductor 7 Final - January 29, 2015 v3.1

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zDA14580

Low Power Bluetooth Smart SoC

Dialog Semiconductor
Dialog Semiconductor

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