|
|
|
부품번호 | W551C020 기능 |
|
|
기능 | Serial Voice Memory | ||
제조업체 | Winbond | ||
로고 | |||
W551CXXX Data Sheet
Table of Contents-
SERIAL VOICE MEMORY
1. GENERAL DESCRIPTION ......................................................................................................... 2
1.1 W551Cxxx Features Description .................................................................................... 2
1.2 W551Cxxx Pad Description ............................................................................................ 3
1.2.1 W551C002/005/010/020/040/060/080 Pad Description....................................................3
1.2.2 W551C160/240/320 Pad Description ...............................................................................4
2. FUNCTION DESCRIPTION ........................................................................................................ 5
2.1 W551Cxxx System Block Diagram ................................................................................. 5
2.2 W551Cxxx Serial Read Mode......................................................................................... 7
2.3 W551Cxxx Self-test Mode .............................................................................................. 9
3. ELECTRICAL CHARACTERISTICS......................................................................................... 10
3.1 W551Cxxx Absolute Maximum Ratings ....................................................................... 10
3.2 W551Cxxx DC Characteristics ..................................................................................... 10
3.3 W551Cxxx AC Characteristics...................................................................................... 11
4. TIMING WAVEFORM ............................................................................................................... 12
5. APPLICATION CIRCUITS ........................................................................................................ 15
6. REVISION HISTORY ................................................................................................................ 17
Publication Release Date: October 3, 2005
- 1 - Revision A2
W551CXXX
1.2.2 W551C160/240/320 Pad Description
PIN NAME
TEST
TEST_OUT
ADDR
I/O DESCRIPTION
I Internal pull-high. Set TEST low to enable "Self-test" function.
Indicates the result of self-test process. “0” indicates a correct result; “1”
O indicates an incorrect result. At Power-On-Reset, it outputs a logic "1"
signal.
I Clock input for shift-in start address;
the first rising-edge signal resets the address counter.
BS
DATA1
DATA2
/CS
CLK
VDD
VSS
I Memory bank selection (for W551C320 use only; W551C240 TBD):
"0": lower 16Mbit, "1": higher 16Mbit.
IO Bi-directional data pin-1 with internal pull-high.
Bi-directional data pin-2 with internal pull-high
IO
used for cascading address and data through the IC.
Active-low chip enable. Determines whether or not to cascade when in
address mode:
I “0”: DATA2 does not have any cascaded chips appended
“1”: DATA2 has cascaded chips appended.
I Clock input for data read-out.
Power Positive power supply pin.
Ground
-4-
4페이지 W551CXXX
2.2 W551Cxxx Serial Read Mode
The default mode is serial read mode.
The address is 24 bits long. The MSB x bits are the page code, and the remaining (24 - x) bits are the
offset address. The address data is shifted, MSB first, into the address counter by the ADDR clock,
and the device is enabled if the page code matches the content of the W551Cxxx page-code cells.
The number of bits in the page code varies by part number and is shown below.
PART # W551C002
DENSITY 256K bits
PAGE CODE 6 bits
W551C005
512K bits
5 bits
W551C010
1M bits
4 bits
W551C020
2M bits
3 bits
W551C040
4M bits
2 bits
W551C060
6M bits
2 bits
W551C080
8M bits
1 bit
PART # W551C160
DENSITY 16M BITS
PAGE CODE 0 BITS
W551C240
24M BITS
0 BITS
W551C320
32M BITS
0 BITS
Note: the W551C160/240/320 do not have a page code.
The first rising-edge signal in the ADDR clock resets the address shift registers. Once the address
data has been shifted into the address counter (and the page code bit[s] verified), the falling-edge of
the CLK clock increments the address counter. As a result, in serial-read mode, the ADDR and CLK
clocks should not be active simultaneously. This is illustrated in the timing diagram below.
ADDR
DATA
CLK
TEST
TEST_
OUT
•••
•••
24
T
Publication Release Date: October 3, 2005
- 7 - Revision A2
7페이지 | |||
구 성 | 총 17 페이지수 | ||
다운로드 | [ W551C020.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
W551C020 | Serial Voice Memory | Winbond |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |