|
|
PDF PAS6352 Data sheet ( Hoja de datos )
| Número de pieza | PAS6352 | |
| Descripción | CMOS VGA IMAGE SENSOR | |
| Fabricantes | Pixart Imaging | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PAS6352 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
PAS6352 Specification
PAS6352 CMOS VGA IMAGE SENSOR
General Description
The PAS6352 is a highly integrated CMOS active-pixel image sensor that has output of 640 x 480 pixels. It
embedded the new FinePixel™ sensor technology to perform the excellent image quality. PAS6352 outputs 10-bit RGB
raw or YUV/YCrCb 4:2:2 or RGB565/555/444 data through a parallel data bus. It is available in CSP package.
The PAS6352 can be programmed to set the exposure time for different luminance condition via I2CTM serial control
bus. By programming the internal register set, it performs on-chip frame rate adjustment and programmable gain control.
Features
§ Active Pixels: 648 x 488 pixels
§ Resolution: 640 x 480 pixels, 1/4” Lens
§ Bayer-RGB color filter array
§ Output format :
l RAW, 10-bit
l YUV/YCrCb 4:2:2
l RGB565/555/444
§ On-chip 10-bit pipelined A/D converter
§ On-chip manual analog gain control
§ Continuous variable frame time & exposure
time
§ I2CTM Interface
§ Support 1.7V~3.3V I/O
§ Power dissipation: operating typ. TBD@ 2.8V
(VGA YUV 60fps parallel-output, without
loading), low power-down dissipation typ./max.
TBD @ 2.8V
§ Automatic Background Compensation
§ ISP function:
l AEC & AGC
l AWB
l Gamma
l Color matrix
l Sharpness
l De-noise
l Color saturation
l Defect compensation
l Lens shading compensation
l Auto de-flicker
l Decimation-AVG and Scaler
l DRC (Dynamic Range Compensation)
l WOI & Sub-sampling
§ Dummy line & pixel timing
§ Output Hsync at Vsync
§ PLL
§ Module size : TBD
Key Specification
Active Pixel
Resolution
Power
Analog
I/O
Core
[ Array diagonal ]
Pixel Size
Lens Chief Ray Angle
Max. Frame rate
Max. input clock
Max. Pixel clock
Sensitivity
Color filter
Exposure Time
Scan Mode
S/N Ratio
Dynamic range
Package
648(H) x 488(V)
640 (H) x 480 (V)
2.8V
1.7V ~ 3.3V
1.8V
1/4” Lens
5.6um * 5.6um
TBD
VGA 60fps
48 MHz
48 MHz, VGA YUV 60fps
TBD
RGB Bayer Pattern
TBD
Progressive
TBD
TBD
CSP
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
1
PixArt Imaging Inc.
E-mail: [email protected]
V0.6, 2012/11/13
1 page  
PixArt Imaging Inc.
PAS6352
CMOS Image Sensor IC
Data Transfer Format
Master transmits data to salve ( write cycle )
l S : Start.
l A : Acknowledge by salve.
l P : Stop.
l RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 –
Read cycle, RW = 0 – Write cycle.
l SUBADDRESS : The address values of PAS6352 internal control registers. ( Please refer to
PAS6352 register description )
During write cycle, the master generates start condition and then places the 1st byte data that are
combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS6352 )
issues acknowledgment, the master places 2nd byte ( Sub Address ) data on SDA line. Again follow the
PAS6352 acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS6352
control register ( address was assigned by 2nd byte ). After PAS6352 issues acknowledgment, the master
can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS6352
sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat
until last byte write. Every control registers value inside PAS6352 can be programming via this way.
Slave transmits data to master ( read cycle )
l The sub-address was taken from previous write cycle.
l The sub-address is automatically increment after each byte read.
l Am : Acknowledge by master.
l Note there is no acknowledgment from master after last byte read.
During read cycle, the master generates start condition and then place the 1st byte data that are combined
slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits
DATA was also placed on SDA line by PAS6352. The 8 bits data was read from PAS6352 internal control
register that address was assigned by previous write cycle. Follow the master acknowledgment, the
PAS6352 place the next 8 bits data ( address is increment automatically ) on SDA line and then transmit
to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is
no longer generated by master but instead by keep SDA line high. The slave ( PAS6352 ) must releases
SDA line to master to generate STOP condition.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: [email protected]
V0.6,
5
2012/11/13
5 Page 
PixArt Imaging Inc.
PAS6352
CMOS Image Sensor IC
2 62 [4:0] R_Shading_CP_R_Delta[4:0] Increment when AE/AG state change
2 63 [3:0] R_Shading_CP_R_NL[3:0] Shading compensation percentage @Normal Light
2 63 [7:4] R_Shading_CP_R_LL[3:0] Shading compensation percentage @Low Light
2 64 [0] R_Contrast_En
Contrast Enable
2 69 [7:0] R_Brightness_LL[7:0]
Brightness @ Low Light
2 6A [7:0] R_Brightness_NL[7:0]
Brightness @ Normal Light
2 9B [1:0] R_ISP_WOI_HSize[9:8]
Output image Hsize
(ISP2_UpdateFlag=1, update )
2 9C [7:0] R_ISP_WOI_HSize[7:0]
Output image Hsize
(ISP2_UpdateFlag=1, update )
2 9D [1:0] R_ISP_WOI_VSize[9:8]
Output image Vsize
(ISP2_UpdateFlag=1, update )
2 9E [7:0] R_ISP_WOI_VSize[7:0]
Output image Vsize
(ISP2_UpdateFlag=1, update )
2 9F [1:0] R_ISP_WOI_HOffset[9:8]
Output image H offset
(ISP2_UpdateFlag=1, update )
2 A0 [7:0] R_ISP_WOI_HOffset[7:0]
Output image H offset
(ISP2_UpdateFlag=1, update )
2 A1 [1:0] R_ISP_WOI_VOffset[9:8]
Output image V offset
(ISP2_UpdateFlag=1, update )
2 A2 [7:0] R_ISP_WOI_VOffset[7:0]
Output image V offset
(ISP2_UpdateFlag=1, update )
2 B0 [7] R_Scaler_X_En
Scaling Down X Enable
(ISP2_UpdateFlag=1, update )
2 B0 [5:0] R_ScaleDenr_X[5:0]
Scaling Down 16/x , 15<x<63
(ISP2_UpdateFlag=1, update )
2 B1 [7] R_Scaler_Y_En
Scaling Down Y Enable
(ISP2_UpdateFlag=1, update )
2 B1 [5:0] R_ScaleDenr_Y[5:0]
Scaling Down 16/x , 15<x<63
(ISP2_UpdateFlag=1, update )
ISP decimation no in X-direction
2 B2 [3:0] R_EncDecimationNo_X[3:0] (ISP_Zoom_UpdateFlag=1, update )
ISP decimation no in Y-direction
2 B2 [7:4] R_EncDecimationNo_Y[3:0] (ISP_Zoom_UpdateFlag=1, update)
2 BF [1] R_UV_Swap
U V Swap
2 BF [2] R_YC_Swap
Y C Swap
2 C0 [3:0] R_RGB565_mode[3:0]
RGB565_mode
2 C0 [5:4] R_Format_Sel
2 C1 [0] R_Vsync_INV
2 C1 [1] R_Hsync_INV
2 C1 [2] R_Pxclk_INV
3 2 [0] R_CCMASign[8]
3 3 [7:0] R_CCMASign[7:0]
Output Data format select
0:YUV 1:RGB565 2:RGB555 3:RGB444
(ISP2_UpdateFlag=1, update )
Vsync inverse
Hsync inverse
Pxclk inverse
ACCM Base matrix coefficient
ACCM Base matrix coefficient
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
E-mail: [email protected]
V0.6,
11
2012/11/13
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet PAS6352.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PAS6352 | CMOS VGA IMAGE SENSOR | Pixart Imaging |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |