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DM74LS670M 데이터시트 PDF




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부품번호 DM74LS670M 기능
기능 3-STATE 4-by-4 Register File
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DM74LS670M 데이터시트, 핀배열, 회로
August 1986
Revised March 2000
DM74LS670
3-STATE 4-by-4 Register File
General Description
These register files are organized as 4 words of 4 bits
each, and separate on-chip decoding is provided for
addressing the four word locations to either write-in or
retrieve data. This permits writing into one location, and
reading from another word location, simultaneously.
Four data inputs are available to supply the word to be
stored. Location of the word is determined by the write
select inputs A and B, in conjunction with a write-enable
signal. Data applied at the inputs should be in its true form.
That is, if a high level signal is desired from the output, a
high level is applied at the data input for that particular bit
location. The latch inputs are arranged so that new data
will be accepted only if both internal address gate inputs
are HIGH. When this condition exists, data at the D input is
transferred to the latch output. When the write-enable
input, GW, is HIGH, the data inputs are inhibited and their
levels can cause no change in the information stored in the
internal latches. When the read-enable input, GR, is HIGH,
the data outputs are inhibited and go into the high imped-
ance state.
The individual address lines permit direct acquisition of
data stored in any four of the latches. Four individual
decoding gates are used to complete the address for read-
ing a word. When the read address is made in conjunction
with the read-enable signal, the word appears at the four
outputs.
This arrangement—data entry addressing separate from
data read addressing and individual sense line — elimi-
nates recovery times, permits simultaneous reading and
writing, and is limited in speed only by the write time (27 ns
typical) and the read time (24 ns typical). The register file
has a non-volatile readout in that data is not lost when
addressed.
All inputs (except read enable and write enable) are buff-
ered to lower the drive requirements to one normal Series
DM74LS load, and input clamping diodes minimize switch-
ing transients to simplify system design. High speed, dou-
ble ended AND-OR-INVERT gates are employed for the
read-address function and have high sink current, 3-STATE
outputs. Up to 128 of these outputs may be wire-AND con-
nected for increasing the capacity up to 512 words. Any
number of these registers may be paralleled to provide n-
bit word length.
Features
s For use as:
Scratch pad memory
Buffer storage between processors
Bit storage in fast multiplication designs
s Separate read/write addressing permits simultaneous
reading and writing
s Organized as 4 words of 4 bits
s Expandable to 512 words of n-bits
s 3-STATE versions of DM74LS170
s Fast access times 20 ns typ
Ordering Code:
Order Number Package Number
Package Description
DM74LS670M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS670N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS006436
www.fairchildsemi.com




DM74LS670M pdf, 반도체, 판매, 대치품
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
Min Max
(Note 8)
Units
VI Input Clamp Voltage
VOH HIGH Level
Output Voltage
VOL LOW Level
Output Voltage
II Input Current @ Max
Input Voltage
VCC = Min, II = −18 mA
VCC = Min, IOH = Max
VIL = Max, VIH = Min
VCC = Min, IOL = Max
IOL = Max, VIH = Min
VCC = Max
VI = 7V
IIH HIGH Level
Input Current
VCC = Max
VI = 2.7V
IIL LOW Level
Input Current
VCC = Max
VI = 0.4V
IOZH
Off-State Output Current with
VCC = Max, VO = 2.7V
HIGH Level Output Voltage Applied VIH = Min, VIL = Max
IOZL
Off-State Output Current with
VCC = Max, VO = 0.4V
LOW Level Output Voltage Applied VIH = Min, VIL = Max
IOS
Short Circuit Output Current
VCC = Max (Note 9)
ICC Supply Current
VCC = Max (Note 10)
Note 8: All typicals are at VCC = 5V, TA = 25°C.
2.4
D, R or W
GW
GR
D, R or W
GW
GR
D, R or W
GW
GR
20
3.4
0.34
30
1.5
0.5
0.1
0.2
0.3
20
40
60
0.4
0.8
1.2
20
20
100
50
V
V
V
mA
µA
mA
µA
µA
mA
mA
Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 10: ICC is measured with 4.5V applied to all DATA inputs and both ENABLE inputs, all ADDRESS inputs are grounded and all outputs are OPEN.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
tPZH Output Enable Time
to HIGH Level Output
tPZL Output Enable Time
to LOW Level Output
tPHZ Output Disable Time from
HIGH Level Output (Note 11)
tPLZ Output Disable Time from
LOW Level Output (Note 11)
Note 11: CL = 5 pF.
From (Input)
To (Output)
Read Select to Q
Read Select to Q
Write Enable to Q
Write Enable to Q
Data to Q
Data to Q
Read Enable to Any Q
Read Enable to Any Q
Read Enable to Any Q
Read Enable to Any Q
RL = 667
CL = 45 pF
CL = 150 pF
Min Max Min Max
40 50
45 55
45 55
50 60
45 55
40 50
35 45
40 50
50
35
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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