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PDF AT45DB021E Data sheet ( Hoja de datos )
| Número de pieza | AT45DB021E | |
| Descripción | SPI Serial Flash Memory | |
| Fabricantes | Adesto | |
| Logotipo |  |
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AT45DB021E
2-Mbit DataFlash (with Extra 64-Kbits), 1.65V Minimum
SPI Serial Flash Memory
Features
Single 1.65V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
Supports RapidS™ operation
Continuous read capability through entire array
Up to 85MHz
Low-power read option up to 15MHz
Clock-to-output time (tV) of 6ns maximum
User configurable page size
256 bytes per page
264 bytes per page (default)
Page size can be factory pre-configured for 256 bytes
One SRAM data buffer (256/264 bytes)
Flexible programming options
Byte/Page Program (1 to 256/264 bytes) directly into main memory
Buffer Write
Buffer to Main Memory Page Program
Flexible erase options
Page Erase (256/264 bytes)
Block Erase (2KB)
Sector Erase (32KB)
Chip Erase (2-Mbits)
Advanced hardware and software data protection features
Individual sector protection
Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Hardware and software controlled reset options
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
200nA Ultra-Deep Power-Down current (typical)
3μA Deep Power-Down current (typical)
25μA Standby current (typical at 20MHz)
4.5mA Active Read current (typical)
Endurance: 100,000 program/erase cycles per page minimum
Data retention: 20 years
Complies with full industrial temperature range
Green (Pb/Halide-free/RoHS compliant) packaging options
8-lead SOIC (0.150ʺ wide and 0.208" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
9-ball Ultra-thin UBGA (6 x 6 x 0.6mm)
8789E–DFLASH–10/2013
1 page  
3. Memory Array
To provide optimal flexibility, the AT45DB021E memory array is divided into three levels of granularity comprising of
sectors, blocks, and pages. Figure 3-1, Memory Architecture Diagram illustrates the breakdown of each level and details
the number of pages per sector and block. Program operations to the DataFlash can be done at the full page level or at
the byte level (a variable number of bytes). The erase operations can be performed at the chip, sector, block, or page
level.
Figure 3-1. Memory Architecture Diagram
Sector Architecture
Sector 0a = 8 pages
2,048/2,112 bytes
Sector 0b = 120 pages
30,720/31,680 bytes
Sector 1 = 128 pages
32,768/33,792 bytes
Sector 6 = 128 pages
32,768/33,792 bytes
Sector 0a
Block Architecture
Block 0
Block 1
Block 2
8 Pages
Block 14
Block 15
Block 16
Block 17
Block 30
Block 31
Block 112
Block 113
Page Architecture
Page 0
Page 1
Page 6
Page 7
Page 8
Page 9
Page 14
Page 15
Page 16
Page 17
Page 18
Sector 7 = 128 pages
32,768/33,792 bytes
Block 126
Block 127
Block = 2,048/2,112 bytes
Page 1,022
Page 1,023
Page = 256/264 bytes
AT45DB021E
8789E–DFLASH–10/2013
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5 Page 
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
6.4 Main Memory Page Program through Buffer with Built-In Erase
The Main Memory Page Program through Buffer with Built-In Erase command combines the Buffer Write and Buffer to
Main Memory Page Program with Built-In Erase operations into a single operation to help simplify application firmware
development. With the Main Memory Page Program through Buffer with Built-In Erase command, data is first clocked
into the Buffer, the addressed page in memory is then automatically erased, and then the contents of the Buffer are
programmed into the just-erased main memory page.
To perform a Main Memory Page Program through Buffer using the standard DataFlash page size (264 bytes), an
opcode of 82h must first be clocked into the device followed by three address bytes comprised of five dummy bits,
10 page address bits (PA9 - PA0) that specify the page in the main memory to be written, and nine buffer address bits
(BFA8 - BFA0) that select the first byte in the Buffer to be written.
To perform a Main Memory Page Program through Buffer using the binary page size (256 bytes), an opcode of 82h must
first be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address bits
(A17 - A8) that specify the page in the main memory to be written, and eight address bits (A7 - A0) that selects the first
byte in the Buffer to be written.
After all address bytes have been clocked in, the device will take data from the input pin (SI) and store it in the Buffer. If
the end of the Buffer is reached, the device will wrap around back to the beginning of the Buffer. When there is a
low-to-high transition on the CS pin, the device will first erase the selected page in main memory (the erased state is a
Logic 1) and then program the data stored in the Buffer into that main memory page. Both the erasing and the
programming of the page are internally self-timed and should take place in a maximum time of tEP. During this time, the
RDY/BUSY bit in the Status Register will indicate that the device is busy.
The device also incorporates intelligent erase and programming algorithms that can detect when a byte location fails to
erase or program properly. If an erase or program error arises, it will be indicated by the EPE bit in the Status Register.
6.5 Main Memory Byte/Page Program through Buffer without Built-In Erase
The Main Memory Byte/Page Program through the Buffer without Built-In Erase combines both the Buffer Write and
Buffer to Main Memory Program without Built-In Erase operations to allow any number of bytes (1 to 256/264 bytes) to be
programmed directly into previously erased locations in the main memory array. With the Main Memory Byte/Page
Program through Buffer without Built-In Erase command, data is first clocked into Buffer, and then only the bytes clocked
into the Buffer are programmed into the pre-erased byte locations in main memory. Multiple bytes up to the page size can
be entered with one command sequence.
To perform a Main Memory Byte/Page Program through the Buffer using the standard DataFlash page size (264 bytes),
an opcode of 02h must first be clocked into the device followed by three address bytes comprised of five dummy bits,
10 page address bits (PA9 - PA0) that specify the page in the main memory to be written, and nine buffer address bits
(BFA8 - BFA0) that select the first byte in the Buffer to be written. After all address bytes are clocked in, the device will
take data from the input pin (SI) and store it in the Buffer. Any number of bytes (1 to 264) can be entered. If the end of the
Buffer is reached, then the device will wrap around back to the beginning of the Buffer.
To perform a Main Memory Byte/Page Program through the Buffer using the binary page size (256 bytes), an opcode of
02h must first be clocked into the device followed by three address bytes comprised of six dummy bits, 10 page address
bits (PA9 - PA0) that specify the page in the main memory to be written, and eight address bits (A7 - A0) that selects the
first byte in the Buffer to be written. After all address bytes are clocked in, the device will take data from the input pin (SI)
and store it in the Buffer. Any number of bytes (1 to 256) can be entered. If the end of the Buffer is reached, then the
device will wrap around back to the beginning of the Buffer. When using the binary page size, the page and buffer
address bits correspond to an 18-bit logical address (A17-A0) in the main memory.
After all data bytes have been clocked into the device, a low-to-high transition on the CS pin will start the program
operation in which the device will program the data stored in the Buffer into the main memory array. Only the data bytes
that were clocked into the device will be programmed into the main memory.
AT45DB021E
8789E–DFLASH–10/2013
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